Conversion Driven Design of Binary to Mixed Radix Circuits

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Conversion Driven Design of Binary to Mixed
Radix Circuits

• Ashur Rafiev, Julian Murphy, Danil Sokolov, Alex
  Yakovlev
• School of EECE, Newcastle University, UK
• ashur.rafiev, j.p.murphy, danil.sokolov,
  alex.yakovlev _at_ ncl.ac.uk

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Outline

• Switching Balanced Codes
• Conversion Driven Design (CDD)
• Motivation
• Conversion Basics
• Bitwise Approach
• Bitwise Gate Grouping Algorithm
• Artificial Combinational Loops Problem
• Operandwise Approach
• Operandwise Gate Grouping Algorithm
• Benchmark Results
• Conclusions

Outline
3
Switching Balanced Codes

• M-of-N data encoding data signal is represented
  with
• N wires
• M of them are active (high)
• Return-to-zero (RTZ) protocol data signals are
  separated with dummy signals (spacers)
• Application areas
• Security
• Asynchronous system design
• Network-on-chip communication

Switching Balanced Codes
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1-of-2 (Dual-Rail) and 1-of-4 Encodings
multi-valued single-rail (binary) dual-rail 1-of-4
0 1 2 3 00 01 10 11 01 01 01 10 10 01 10 10 0001 0010 0100 1000
NULL spacer 00 00 0000
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Outline

• Switching Balanced Codes
• Conversion Driven Design
• Motivation
• Conversion Basics
• Bitwise Approach
• Bitwise Gate Grouping Algorithm
• Artificial Combinational Loops Problem
• Operandwise Approach
• Operandwise Gate Grouping Algorithm
• Benchmark Results
• Conclusions

Outline
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Conversion Driven Design Motivation

• Higher radix signals consume less power and
  reduce cross-talk effect
• Require multi-valued logic synthesis
• Some tools and techniques already exist (e.g.
  MV-SIS)
• Moving away from the RTL design flow is
  frequently frowned upon by industry

• Reuse existing popular design tools for
  multi-valued system design

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Conversion Driven Design Flow
Convert to mixed radix component level design
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Conversion Basics
Original binary datapath is given as a structural
HDL netlist.
Pairs of binary signals can be grouped into
quaternary.
Certain part of the circuit may remain binary.
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Conversion Basics

• Signal converters
• A splitter converts one quaternary signal into
  two binary.
• A mixer converts two binary signals into one
  quaternary.
• The way the signals (gates) are grouped
  determines the efficiency of the conversion,
  therefore the conversion problem corresponds
  directly to the gate grouping problem.

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Outline

• Switching Balanced Codes
• Conversion Driven Design
• Motivation
• Conversion Basics
• Bitwise Approach
• Bitwise Gate Grouping Algorithm
• Artificial Combinational Loops Problem
• Operandwise Approach
• Operandwise Gate Grouping Algorithm
• Benchmark Results
• Conclusions

Outline
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Bitwise Gate Grouping
AA0, A1 BB0, B1 Q Q0, Q1 Q AB Q0
A0B0 Q1 A1B1
a bitwise quaternary component
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Bitwise Gate Grouping Algorithm

• Uses heuristics to extract bitwise meaning of
  signals from the flat netlist.
• Input and output port grouping is given
• Algorithm is iterative, based on breadth-first
  search
• Bitwise Regularity Ratio is used as an estimation
  criteria. It is calculated for each gate pair on
  each iteration.
• Bitwise Regularity Ratio (BRR) depends on how
  many quaternary links a pair of gates can form
  with respect to the state of the conversion on
  the given iteration.

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Bitwise Gate Grouping Algorithm Example
original circuit
converted circuit
mixed radix components are shown as black boxes
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Artificial Combinational Loops

• Combinational loops can appear during the bitwise
  conversion while the original circuit is free of
  combinational loops.
• Need special methodology to handle. Problems
• If mixers wait for valid data from both inputs
  deadlock.
• If mixers produce output regardless to spacers
  invalid output.
• A signal should pass artificial combinational
  loop exactly 2 times before it produce a valid
  output.

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Bitwise Gate Grouping

• Disadvantages of the algorithm
• Computational cost O(N) 2N2log22N, N is a
  number of gates in the original circuit.
• Disadvantages of the approach
• Inefficient for circuits without bitwise nature
  of signals, e.g.S-boxes.
• The algorithm can produce combinational loops.
• Bitwise (naive) approach is inefficient for CDD.

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Outline

• Switching Balanced Codes
• Conversion Driven Design
• Motivation
• Conversion Basics
• Bitwise Approach
• Bitwise Gate Grouping Algorithm
• Artificial Combinational Loops Problem
• Operandwise Approach
• Operandwise Gate Grouping Algorithm
• Benchmark Results
• Conclusions

Outline
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Operandwise Gate Grouping
a bitwise quaternary component
an operandwise quaternary component

• Bitwise grouping is derived from the functional
  meaning of signals.
• Operandwise grouping is derived from the
  structural positioning of gates works with
  2-input gates only.

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Binary Trees Approach
For binary tree structures within a netlist we
can group inputs and outputs of gates to perform
an operandwise grouping.
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Binary Trees Approach
Signals cannot be shared between groups, because
it leads to duplication of gates. Gates with
multiple fanout block operandwise grouping.
Remain binary
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Quaternary-to-Binary Gates (Q/B Gates)
Q/B gate a gate with one quaternary input and
one binary output.
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Quaternary-to-Binary Gates (Q/B Gates)

• A Q/B gate is a mixed radix component.
• A Q/B gate is an incomplete operandwise group.
• It can replace a splitter followed by a binary
  gate.

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Operandwise Gate Grouping Algorithm

• Phase I group all signals regardless of gate
  fanouts (some gates will be duplicated).
• Output ports can be grouped arbitrarily.
• Phase II analyse duplicates and discard groups
  leading to duplication.
• Phase III insert signal converters and Q/B
  gates.
• Computational cost of the algorithm is O(N) 3N,
  where N is a number of gates in the original
  circuit.

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Operandwise Gate Grouping Algorithm Example
original circuit
converted circuit
Phase I
Phase II
Phase III
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Operandwise Gate Grouping

• Advantages of the algorithm
• Low computational cost.
• It is highly modular one can add more passes to
  the algorithm to increase efficiency of the
  conversion.
• Disadvantages of the algorithm
• Can produce significant fractioning of binary
  and quaternary parts of the circuit increasing
  the number of signal converters required.

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Benchmark Results
circuit dual-rail dual-rail dual-rail mixed radix dual-rail, 1-of-4 mixed radix dual-rail, 1-of-4 mixed radix dual-rail, 1-of-4
circuit switching wires switching energy switching energy switching wires switching energy switching energy
circuit switching wires average std. dev switching wires average std. dev
2-bit adder 20 11.13 0.2661 14 10.66 0.0000
16-bit ripple carry adder 160 86.31 0.9803 84 75.72 0.0000
4-bit multiplier 56 30.08 0.5247 58 38.72 0.1074
Kasumi S-box7 250 139.13 3.4908 264 144.98 0.6993
Kasumi S-box9 256 146.51 3.7947 264 137.12 1.2070
Kasumi S-box9 300 169.56 1.3448 326 187.96 0.7809
AES S-box 1594 818.56 1.1914 1640 1116.03 0.4870
original single-rail circuits were optimised in
Synopsys.
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Outline

• Switching Balanced Codes
• Conversion Driven Design
• Motivation
• Conversion Basics
• Bitwise Approach
• Bitwise Gate Grouping Algorithm
• Artificial Combinational Loops Problem
• Operandwise Approach
• Operandwise Gate Grouping Algorithm
• Benchmark Results
• Conclusions

Outline
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Conclusions

• Conversion driven design technique was suggested
  in order to reuse popular EDA tools for MVL
  synthesis.
• Binary and quaternary mixed radix was selected to
  improve the efficiency of the conversion.
• Two conversion (gate grouping) algorithms were
  implemented and analysed.
• Bitwise approach is not efficient for CDD
• Operandwise approach is fast and flexible but not
  efficient enough in terms of saving switching
  energy.
• Future work
• Improve operandwise component implementations.
• Add more heuristics to the operandwise algorithm
  to increase the efficiency of the conversion.

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The End

• Thank you!
• Questions?