Paper Discussion

1
Paper Discussion Reim Doumat Thomas
Watteyne  Simulation of Soc Architectures 
2
 Overview of the Ptolemy Project  Jul.
2003  Modeling and Simulation Issues of
Programmable Architectures  Mar. 2001  Rapid
System-Level Performance Evaluation and
Optimization for Application Mapping onto SoC
Architecures  Oct. 2002  Modeling and
Simultaion of Embedded Processors Using Abstract
State Machine  Mar. 2001
3
General Overview
Introduction to Modeling, Design and Simulation
Rapid System-Level Performance Evaluation and
Optimization for Application Mapping onto SoC
Architectures
Modeling and Simulation of Embedded Processors
Using Abstract State Machines
4
Part I Introduction to Modeling, Design and
Simulation
5
Overview

1. Introduction
2. Machine and Hardware Description Languages, the
   LISA example
3. Models of computation, the Ptolemy example

6
Introduction Push-pull effect Definitions MDL,
HDL Computation Models
The push-pull effect
Designer productivity
New applications
Semiconductor technology
!!
System complexity
Time-to-market
7
Introduction Push-pull effect Definitions MDL,
HDL Computation Models
The push-pull effect

• productivity
• re-usability
• flexibility

In embedded system design
? Effective design phase
8
Introduction Push-pull effect Definitions MDL,
HDL Computation Models
Definitions

• Modeling representing an architecture
  (mathematical model, constructive model)
• Design defining an architecture
• Simulation executable model

9
Introduction MDL, HDL Why LISA ? Overview LISA Val
idation Computation Models
Why LISA ?
ASIC, DSP processors
Language for Instruction Set Architecture
Electronic systems
Programmable Architecture

• Code generation and simulation tools
• simulator
• assembler
• linker
• graphical debugger

10
Introduction MDL, HDL Why LISA ? Overview LISA Val
idation Computation Models
Programmable Architecture overview
ex POSIX
Machine Description Language (ex LISA)
Instruction Set
Hardware Description Langage (ex VHDL, Verilog)
11
Introduction MDL, HDL Why LISA ? Overview LISA Val
idation Computation Models
LISA
Software developpement environment
12
Introduction MDL, HDL Why LISA ? Overview LISA Val
idation Computation Models
Validation

• simulation speed (x1000 instruction/cycles per
  second)
• Use of compilation simulation

• assembler/linker speed
• equivalent

LISA ? VHDL ?
13
Introduction MDL, HDL Computation Models
Computation Models
 Overview of the Ptolemy Project  Jul. 2003
14
Ptolemy II - Introduction
Introduction MDL, HDL Computation
Models Introduction Ptolemy Project Models Choosin
g Facts
?
Ptolemy II (1996to date)

• Introduces
• Domain polymorphism
• Modal Models

Ptolemy Classic (19901997)
Gabriel (19861991)
15
Introduction MDL, HDL Computation
Models Introduction Ptolemy Project Models Choosin
g Facts
Ptolemy - Introduction

• Definition The project studies
• modeling,
• simulation,
• design of concurrent, real-time, embedded
  systems
• Characteristics
• - Components built on top of Java compiler (Soot)
  
• - XML as data representation
• - Concept of migrating models

16
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Ptolemy Project

• Complete separation of the abstract synthax
  from the semantics.
• Synthax, Actor-Oriented design
• - models, actors, ports, parameters, channels
• - represented graphically, XML or by program with
  specific API
• Semantics, the physical laws
• - models constructed under model of computation
• - choice of model of computation has deep impact
  on implementation
• - interoperability of executable models
• - hierarchical mix of domains

17
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Example of the actor oriented design
18
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Ptolemy II- Modeling and Design
19
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Ptolemy Modeling Design
Focus on - Embedded software - Actor oriented
design (Version 4.0.1) - Architecture Design 1)
Components designed to be domain
polymorphic 2) Interaction mechanisms among
domains 3) Development of a meta-model
describing models of computation
20
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Models of Computation

• At least 12 different models of computation
• Variety of models because
• time (continuous, discrete, causal)
• concurency, interactions
• different underlying mathematical models

21
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Models of Computation

• Component Interaction (Demand-Driven, e.g. Web
  Browsers)
• Communication Sequential Processes (use of
  rendez-vous)
• Continuous Time
• Discrete-Events
• Distributed Discrete Events
• Discrete Time
• Finite-State Machines
• Process Networks
• Synchronous Dataflow
• Giotto (hard real time)
• Synchronous/reactive
• Timed Multitasking

22
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Choosing a Model of Computation

• Most designer faced to only one or two
• Choice is very important (time, event, etc.)
• Unifying not possible ... (complex)

23
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Ptolemy II Whats the Architecture?

• Core packages support data model and actor
  model
• User Interface packages support XML file format
  (MoML)
• Library packages define actors to be domain
  polymorphic
• domains subpackages of ptolemy domains package

24
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Ptolemy II some capabilities

• Higher level concurrent design in Java
• Better modularization through the use of packages
• Complete separation of the abstract syntax from
  the semantics
• Domain-polymorphic actors

25
Introduction MDL, HDL Computation
Models Introduction Ptolemy Models Choosing Facts
Ptolemy in facts

• 3rd generation Ptolemy II
• Java as a programming language
• Visual synthax
• Set of packages

26
Part II Rapid System-Level Performance
Evaluation and Optimization for Application
Mapping onto SoC Architectures October
2002 Sumit Mohanty, Viktor K. Prasanna
27
Introduction GenM HiPerE MILAN conclusion
Introduction
GenM
Evaluation optimization of performance During
application design
HiPerE
Estimation at the system level
MILAN
Estimation of specific component performance
28
Introduction GenM HiPerE MILAN conclusion
Generic Model for Application Mapping onto SoC
Architecture
DVS (Dynamic Voltage Scaling)
Components of the GenM Model
29
Introduction GenM HiPerE MILAN conclusion
Why to use GenM?

• Rapid estimation of performance.

• Development of efficient application designs
• (High Level abstraction).

• Development of optimization techniques for
  mapping application onto SoC architecture.

30
Introduction GenM HiPerE MILAN conclusion
HiPerE (High-Level Performance Estimator)
-Interpretive simulator
-system-level performance estimation
HiPerE
31
Component Specific Performance Estimation MILAN(Mo
del based Integrated simuLAtioN
Introduction GenM HiPerE MILAN conclusion
MILAN
Component Specific Estimates
Low-level simulator
Component specific Performance Estimation using
MILAN
32
Introduction GenM HiPerE MILAN conclusion
Performance estimation includes?

• Cost for execution

• Data access

• Memory activation

• reconfiguration

33
Introduction GenM HiPerE MILAN conclusion
Application Optimization Using MILAN
Hierarchical Simulation for DES in MILAN
34
    
Introduction GenM HiPerE MILAN conclusion
Application Optimization Using MILAN
    
35
Introduction GenM HiPerE MILAN conclusion
Conclusion
By using (GenM,HiPerE,MILAN) solve
these problems

• Estimation of system-level performance for SoC
  architectures.
• Lack of high-level abstraction for SoC
  architectures.
• Lack of standard interface between different
  component simulators.

36
Part III Modeling and Simulation of Embedded
Processors Using Abstract State Machines March
2001 Dirk Fischer, Jurgën Teich, Ralph Weper
37
Overview

1. Architecture/compiler co-design
2. Abstract State Machines
3. The BUILDABONG project
4. Papers Interest

38

1. Architecture/Compiler co-design in ASIPs

39
co-design Needs Process Related
work ASMs BUILDABONG Interest
The needs
- ASIP ASAP ?
Application Specific Instruction Set Processors
As soon as possible

• customized processors
• special applications (signal processing)

• time to market
• optimal application/processor tradeoff

ASIP
ASAP
40
co-design Needs Process Related
work ASMs BUILDABONG Interest
Process

• complex instruction set
• simple application

• Simple instruction set
• Complex application

More design / manufacturing process costs
More computation time, more memory
Architecture/compiler co-design
Application
Processor
Exploration Simulation
41
co-design Needs Process Related
work ASMs BUILDABONG Interest
work on architecture/compiler co-design

• LISA University of Aachen, Germany

Compiled simulator ? 100K instructions per second

• CASTEL

VHDLRTL
DATA PATH MODELextended FSM

• EXPRESSION University of California, USA

Retargetable compiler
V-SAT Graphical Design Environment
EXPRESSION model
Cycle accurate simulator
42

1. Abstract State Machines

43
co-design ASMs Mathematics Modeling Advantages BUI
LDABONG Interest
The Mathematics
lt ?
lt ?
gt ?
gt ?
?
?
?
universe

• Functions
• Relations

? Algebra
structure
44
co-design ASMs Mathematics Modeling Advantages BUI
LDABONG Interest
The Mathematics
Abstract State Machine
? (V, f1, f2, , fn)
Finite vocabulary
Finite set of n-ary functions over V
(State of M algebra over V )
Initial state S0 set of transition rules P ASM
45
co-design ASMs Mathematics Modeling Advantages BUI
LDABONG Interest
The Mathematics
Transition Rule
No relations ? boolean value
If ltcondgt then ltRulegt endif
Update rule f(t1, t2, , tn) t
46
co-design ASMs Mathematics Modeling Advantages BUI
LDABONG Interest
The Mathematics
Operationnal semantics
No cycling
Update rule
R
R
R
Si
Si2
Sn
Si1
state
Terminal state
47
co-design ASMs Mathematics Modeling Advantages BUI
LDABONG Interest
Modeling processors with ASMs

• cycle accurate model, register transfer level
• a register tranfer is conditionned (mode
  registers, instruction bits)
• guarded register transfer paterns (Leupers)

If ltregister_transfer_conditiongt then ltregister_tr
ansfer_patterngt endif
? ASMs
48
co-design ASMs Mathematics Modeling Advantages BUI
LDABONG Interest
Advantages

• short description (ARM7, 200 lines XASM)
• readability
• cycle accuracy
• simulation speed (?)
• XASM environment supports C-libraries (irregular
  arithmetic operations on arbitrary large
  word-lengths)
• natural mathematical tool

49

1. The BUILDABONG project

50
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
General View
Explorer
ANSI C Program
Graphical input
Retargetable Compiler
Instruction Set Description
ASM
Assembler Program
library
Simulator Generator (Gem-Mex)
Parser Linker Loader
Simulator
51
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
Graphical Architecture Editor

• libraries
• hierarchical

52
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
XASM-code generation
53
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
XASM-code generation
Library include
54
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
XASM-code generation
Function declaration
55
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
XASM-code generation
Sequential element initialization
56
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
XASM-code generation
Guarded update rules (memory and registers)
?
57
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
Automatic Simulator Generator
?
58
co-design ASMs BUILDABONG General
view Editor XASM Simulator Future work Interest
To-Do list
59

1. The papers interest

60
co-design ASMs BUILDABONG Interest
Criticism

• meets the demand
• structured project
•  natural  modeling tool
• but proprietary graphical language
• openings
• Fine-tuning of the compiler (different needs)
• Conversion tools with HDLs