The%20Development%20of%20Psec-Resolution%20TDC%20for%20Large%20Area%20TOF%20Systems

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The Development of Psec-Resolution TDC for Large
Area TOF Systems

• Fukun Tang
• Enrico Fermi Institute
• University of Chicago

With Karen Byrum and Gary Drake (ANL) Shreyas
Baht, Tim Credo, Henry Frisch, Harold Sanders and
David Yu (UC)
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Major advances for TOF measurements
From H. Frisch
Output at anode from simulation of 10 particles
going through fused quartz window- T. Credo, R.
Schroll
Jitter on leading edge 0.86 psec

• Ability to simulate electronics and systems
• to predict design performance

3
Requirement Psec-Resolution TDC
MCP_PMT Output Signal
Start
500pS
Reference Clock
Stop
Tw
1 ps Resolution Time-to-Digital Converter!!!
4
Diagram of MCP-PMT ElectronicsFrom Harold
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Approaches Possibilities
(1) TAC-ADC
1/4
Zero-walk Disc.
TAC
Driver
11-bit ADC
Receiver
PMT
2 Ghz PLL
REF_CLK
4x1Ghz PLL
psFront-end (Timing Module Option 1)
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TAC-ADC Simulation Result

• Electronics with typical gate jitters ltlt 1 psec

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Approaches Possibilities
(2) Time Stretcher
1/4
Zero-walk Disc.
Stretcher
Driver
11-bit Counter
Receiver
PMT
CK5Ghz
2 Ghz PLL
REF_CLK
psFront-end (Timing Module Option 2)
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Time Stretcher Simulation Result
x200 Stretched Time Interval (Output Signal )
Stretched Time 274ns (pedestal74ns)
1ns Time Interval (Input Signal)
0 50ns 100ns 150ns 200ns
250ns 300ns
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VCO Submission of Oct. 2006

• Ultimate Goal
• To build TDC with 1 pSec Resolution for Large
  Scale of Time-of-Flight Detector.
• Primary Goal
• To build 2-Ghz VCO, key module of PLL that
  generates the TDC reference signal
• Cycle-to-Cycle Time-jitter lt 1 ps
• To evaluate IHP SG25H1/M4M5 Technology for our
  applications
• To gain experiences on using Cadence tools
  (Virtuoso Analog Environment)
• Circuit Design (VSE)
• Simulation (Spectre)
• Chip Layout (VLE, XLE, VCAR)
• DRC and LVS Check (Diva, Assura, Calibre)
• Parasitic Extraction (Diva)
• Post Layout Simulation (Spectre)
• GDSII Stream out
• Validation
• Tape Out

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Diagram of Phase-Locked Loop
CP
Fref
I1
Uc
PD
VCO
F0
LF
I2
1N
PD Phase Detector CP Charge Pump LF Loop
Filter VCO Voltage Controlled Oscillator
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IHP (SG25H1) 0.25mm SiGe BiCMOS Technology

• 0.25mm BiCMOS technology
• 200Ghz NPN HBT (hetero-junction bipolar
  transistor)
• MIM Capacitors (layer2-layer3) ( 1f/1u2 )
• Inductors (layer3-layer4)
• High dielectric stack for RF passive component
• 5 metal layers (Al)
• Digital Library Developing

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SG25 Process Specification
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2-GHz BiCMOS VCO Schematic
Negative Resistance and Current-Limited Voltage
Control Oscillator with Accumulating PMOS Varicap
and 50W Line Drivers
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V-F Plot (3 model cases _at_ 27C-55C)
Frequency
Temperature 27C-55C Supply VDD2.5V
VControl varied 0.18V
VControl
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Phase Noise ( 3 model cases _at_ 27C)
_at_100KHz offset
Worst
Best -89.94 dBc/Hz
Typical -89.58 dBc/Hz
Worst -89.90 dBc/Hz
Typical
Best
Temperature 27C Supply VDD2.5V
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Calculation of Cycle-to-Cycle Jitter
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2-GHz VCO Performance Summary (1)
T27C f0 2 GHz
phase noise
dBc/Hz_at_100K offset
Vcontrol (V) Itail (mA) Vpp (mV) Icc (mA) Pw (mW) Phase Noise
Best 1.54 10.90 635 33.92 85.0 -89.75
Typical 1.60 8.83 573 27.63 67.5 -89.54
Worst 1.68 7.48 524 22.31 56.0 -89.18
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2-GHz VCO Performance Summary (2)
T55C f0 2 GHz
phase noise
dBc/Hz_at_100K offset
Vcontrol (V) Itail (mA) Vpp (mV) Icc (mA) Pw (mW) Phase Noise
Best 1.56 10.50 628 34.48 86.3 -89.15
Typical 1.64 8.63 571 28.05 70.0 -88.72
Worst 1.70 7.38 521 22.57 56.5 -88.56
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Virtuoso XL Layout View
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Virtuoso Chip Assembly Router View
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Diagram of Post Layout Simulation
Schematic
Analog_extracted
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Transit Analysis Comparison of Schematic and
Post Layout Simulations
Outputs_at_50W loads
Schematic
Post Layout
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V-F Plot Comparison of Schematic and Post Layout
Simulations
Frequency
Post Layout
Schematic
Vcontrol
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Phase Noise Post Layout SimulationsVDD2.5V
Temp.27C, 55C
Phase Noise _at_100KHZ offset
27C -89.40 dBc/Hz (Sch -89.75)
55C -88.90 dBc/Hz (Sch -89.15)
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Conclusion

• (1) VCO time-jitter met our requirement.
• (2) Post layout simulation matched schematic
  simulation very well.
• (3) Some problems we have encountered with pcell
  library, layout, DRC, LVS and auto-routing
  functionalities.
• (4) Ready for October Submission.