Core-Selectability in Chip-Multiprocessors

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Core-Selectability in Chip-Multiprocessors

• Hashem H. Najaf-abadi
• Niket K. Choudhary
• Eric Rotenberg

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Dividing the DesignA definition
Processing Cores
All levels of cache Interconnect
Ports to Memory and IO
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What this Talk is About

• How to improve performance of a CMP

by enabling exploitation of the full
potential of the interconnection
the interconnect is not fully utilized by all
workloads
by improving the processing
if it is, theres nothing to gain here
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The Provisioning Factor Balance in provisioned
resources
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The Provisioning Factor Balance in provisioned
resources
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The Underutilization Factor Interconnect not
fully utilized by all applications
workloads that depend the most on interconnect
have a louder say in what a well-provisioned
design constitutes
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The One-size-fits-all Factor A single solution
has limited performance
Changing these trade-offs will improve
performance for some workloads and degrade it for
others.
Hes not much for a conversation.
But if he was, it would be a conversation about
saving you execution time.
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The Shrinking Factor Progressively less die area
for the cores
better return on increasing the interconnection
resources

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The Shrinking Factor Progressively less die area
for the cores
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The Shrinking Factor Progressively less die area
for the cores
Intel
8088
Intel386
100
Intel
Intel
IBM
90
8086
80286
Intel 486DX
Power3
80
Intel
70
Intel
Pentium IV
Pentium
Intel
60
Pentium III
50
IBM
IBM
Power4
Power5
Intel Core Duo
40
30
IBM Power6
Niagara-2
-
-
20
Niagara-1
10
1990
2010
2000
2005
1995
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The Diversity Factor Can provide diversity in
the core designs
Single Core Design
Optimized for all workloads
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The Diversity Factor Can provide diversity in
the core designs
Heterogeneous Cores
Optimized for workload
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Core-Selectability
Core-Selectability
Optimized for workload.
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Core-Selectability
Selectability
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Recap
Port Sharing
can improve performance without increasing
power density
results in a homogeneous design
can reduce verification effort by splitting up
workload space
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Core-SelectabilityRemains homogeneous at a high
level
CMP
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Empirical EvaluationBased on Fabscalar

• A library of the synthesized implementation of
  different configurations for different
  microarchitectural units of a contemporary
  superscalar processor.

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The selection of cores
Core-U Core-A Core-B
FETCH STAGES 4 3 5
DECODE STAGES 1 1 1
RETIRE STAGES 2 2 2
ISSUE WIDTH 3 2 5
ROB SIZE 512 1024 512
IWINDOW SIZE 64 128 32
Clock period .6ns .6ns .6ns
normalized exec. time
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On Individual Benchmarks
normalized execution time
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The Effect of Selectability
normalized exec. time
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Under Different Task Arrival Patterns
Average task turnaround time for (a) normal
traffic, and (b) bursty traffic.
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Overhead of Reconfigurability
Issue-Q size Wakeup Delay Select Delay Wake Select Delay Reconfig. Delay
16 0.55ns 0.54ns 1.09ns 1.55ns
32 0.63ns 0.59ns 1.38ns 1.89ns
64 0.67ns 0.65ns 1.62ns 2.10ns
128 0.82ns 0.76ns 2.00ns 2.30ns
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Implementation of Port Sharing
26ps added propagation delay
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Overhead of Reconfigurability

• With reconfigurability, change is implemented
  within a core with complex coupling between
  pipeline stages.
• With Core-Selectability, change is implemented at
  the core level with less complex
  coupling between core and interconnect.

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• Thank you

Its as if he knows you like to save execution
time.