Time-Memory Scheduling and Code Generation of Real-Time Embedded Software

1
Time-Memory Scheduling and Code Generation
ofReal-Time Embedded Software

• Chuen-Hau Gau and Pao-Ann Hsiung
• National Chung Cheng University
• Chiayi, Taiwan, R.O.C.

8th International Conference on Real-Time
Computing Systems and Applications, March 18-20,
2002, Tokyo, Japan
2
Outline

• Introduction
• Previous Work
• Real-Time Embedded Software Synthesis
• ATM VPN Server Example
• Conclusions

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Introduction

• Embedded systems abound in human daily life
• We interact with embedded systems in
• our homes,
• at offices,
• at labs,
• on transportations,
• in communications,
• Due to this interaction with humans, most
  embedded systems are also REAL-TIME systems
• And, software accounts for more than 70
  functionalities in a real-time embedded system

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What is an embedded system?

• Installed in a larger system
• Dedicated task
• Small Memory Space (200400 KB)
• Low Processing Power (100200 MHz)
• Unstable Environment (mobile, )
• Reactive
• Real-Time

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Embedded System Examples
research lab equipments
space crafts
factory automation
office equipments
home appliances
medical instruments
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Embedded System Architecture
7
Design Issues and Solution
Proposed Solution
8
Previous Work

• Formal Software Synthesis
• Safe Petri-Nets (PN) ? Quasi-Static Scheduling
  (QSS) Lin DATE98, DAC98
• Free-Choice PN ? Net Decomposition QSS Sgroi
  DAC99
• Codesign FSM ? POLIS Balarin ICCD99
• Non-timed multi-rate PN ? Reachability
  graphCortadella et al DAC00
• Time Free-Choice PN ? QSS RTS or FIBS Hsiung
  CODES01, FORTE01

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Real-Time Embedded Software (RTES) Model

• Real-Time Embedded Software is specified as a set
  of Colored Time Petri Nets (CTPN)
• Allows explicit modeling of
• Timing Constraints
• Memory Usages
• No free-choice restriction!
• Larger domain of real-time embedded applications!

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Colored Time Petri Nets
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Colored Time Petri Nets

• A CTPN is a 6-tuple (P,T, C, ?,M0,?) such that
• P is a finite set of places,
• T is a finite set of transitions, P ?T ? ?, P ?T
  ?,
• C is a set of colors associated with each token
• ? (P ?T ) ? (T ?P ) ? 2N?C, a set of weighted
  arcs such that each arc is associated with a set
  of integer-color pairs,
• M0 P ? 2N?C, the initial marking,
• ? (t ) (?, ?), t ?T, ? Earliest Firing Time,
  ? Latest Firing Time.

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CTPN Marking

• A marking is a vector
• M ltNC1, NC2, , NCPgt
• where NCi is a set of integer-color pairs
  representing the non-negative number of colored
  tokens in place pi.
• 2 attributes are associated with each M
• (1) a time-stamp ?(M)
• (2) a memory-usage ?(M)

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Valid Firing (System Execution)

• A transition t is said to be enabled at time ? in
  a marking M with time-stamp ?(M) if
• (1) ?(pk, t) ? NCk, ? ?(pk, t) ??, k? 1, ,P,
• (2) ? ? ?(M) ? ?? (t)
• The firing of a transition t at time ? in a
  marking M with time-stamp ?(M) is called a valid
  firing if
• Transition Deadline
• ??(t) ? ? ??(M) ? ??(t)
• Memory Constraint
• ?(M') ? ?max
• where M' is the marking obtained by firing t in
  M and ?max is the maximum amount of memory
  available.

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RTES Synthesis Problem

• Target Problem
• Real-Time Embedded Software Synthesis
• Given
• a set of CTPN S Ai i 1,2,,n,
• an upper-bound ?max on memory space, and
• a set of real-time constraints CTPN periods,
  deadlines
• software code is to be generated such that
• it can be executed on a single processor,
• it uses memory less than or equal to ?max, and
• it satisfies all EFT, LFT, and real-time
  constraints.

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RTES Synthesis Algorithm

• Choice Set
• H t2, t3, t4

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RTES Synthesis Algorithm

• Exclusion Set
• H t2, t3, t4
• Merging of all
• non-disjoint
• choice sets

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RTES Synthesis Algorithm

• Time-Memory Scheduling
• A schedule (sequence of firing transitions) is
  valid if the following are satisfied
• Transition deadline
• CTPN deadline
• Memory bound
• Incomplete exclusion sets are deleted (because
  corresponding code will be illegal)

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RTES Synthesis Algorithm

• Transition Deadline Satisfaction
• Assume transition t
• enabled at marking M with time-stamp ?(M)
• fired at marking M? with time-stamp ?(M?),
• then it must satisfy
• ?(M?) - ?(M) ??(t) ? ??(t)

transition deadline
transition execution time
token age
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RTES Synthesis Algorithm

• CTPN Deadline Satisfaction
• Assume transition t
• fired at marking M?
• ?(M?) ??(t) ? d

CTPN deadline for current task
transition execution time
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RTES Synthesis Algorithm

• Memory Bound Satisfaction
• Assume transition t
• fires and CTPN reaches marking M?
• ?(M?) ? ?max

memory bound
memory usage
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RTES Synthesis Algorithm

• while( Tree ! 0 )
• if( Entire Tree Marked ) CodeGen()
• if( Current Node Is Spawned )
• Current Node Delete Incomplete Exsets
• if Current Node Has Marked Child
• Current Node Delete Other Child, Mark, Go
  Parent
• if(Child SELECT() null)
• Current Node Delete Current and Go Parent
• else
• Current Node Go Child
• else
• if(Current Node Is A CompleteSchedule)
• Current Node Mark and Go Parent
• else
• Current Node Spawn

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RTES Synthesis Algorithm

• Memory Estimation
• Global Memory ?G(R), R tree
• Local Memory maxt?M (?L(t)), t transition,
  M marking
• Buffer Memory
• Total Memory

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Code Generation

• A real-time process for each independent task,
  i.e., each reachability tree
• tasks is minimal ( independent tasks)

Source Transitions in TFCPN
Main Program
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Code Generation Algorithm

• Extract( CNode )
• if( CNode is leaf ) // no child
• Code getCode(CNode)
• Code return
• else if( CNode is branching ) // multi-child
• Code getBranchCode(CNode)
• for each child node CNode.ci
• Extract(CNode.ci)
• else // one child
• Code getCode(CNode)
• Extract(CNode.child)
• return(Code)

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ATM VPN Server

• ATM switching nodes interconnect LANs via an ATM
  backbone.
• An ATM server
• temporarily stores input cells from VCCs (Virtual
  Channel Connections), and
• forward VCC cells to the VPCs (Virtual Path
  Connections) by identifying cell headers.

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(No Transcript)
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Functionalities of ATM VPN

• Message Selective Discarding (MSD)A message
  discarding technique that avoids buffer overflow
  by discarding selected incoming cells
• Weighted Fair Queuing (WFQ)A bandwidth control
  policy for outgoing flows
• Thus, there are TWO independent tasks!

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ATM VPN Server
PUSH
Message Selective Discarding
VCC cell
WFQ scheduling
INSERT
Cell Extract
Counter
TICK
POP
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CTPN model of MSD in ATM
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CTPN models of WFQ, Extract
LAST BW gt GLOBAL_TIME ?
READ_LAST
t14
Y
p25
p27
p29
P30
p26
p28
N
INSERT_CELL
SCHEDULE_WFQ
t13
READ_BW
t15
POP
t19
t17
TICK
t16
SCHEDULE_WFQ
p36
IN?
p33
Qlength0?
N
N
p32
p31
READ_SORTER
N
Y
p35
p39
p37
p38
p34
II1
Y
Y
I0
CHECK_QLENGTH
COMPUTE_OUT_TIME
t18
CELL_OUT_TIME lt GLOBAL_TIME?
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Reachability
Tree for MSD

• Schedule Results
• 49 markings
• 14 schedules
• 66 instructions
• 12 Kbytes Memory

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Reachability Trees for WFQ and Extract

• Schedule Results
• WFQ
• 9 markings
• 2 schedules
• Extract
• 13 markings
• 4 schedules

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Scheduling Results

• Both MSD and Extract call WFQ (2 schedules)
• MSD Task
• schedules 14 ? 2 28
• Extract Task
• schedules 4 x 2 8

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Conclusions

• A synthesis method for real-time embedded
  software was presented
• No free-choice restriction on model
• Explicit time and data modeling
• Both real-time constraints and memory constraints
  are considered for scheduling
• Minimal number of tasks in generated code
• Can be used for prototyping platforms