Microprocessors I

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Microprocessors I

• Intel MCs51 Introduction

CS-00871 Prof. Msc. Ivan A. Escobar iescobar_at_itesm
.mx
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Introduction

• PCs, microprocessor based systems, are much more
  visible.
• Embedded control with microcontrollers vastly
  outnumber uP systems.
• Automotive
• Toys
• Appliances
• Consumer Electronics

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History of Microcont vs Microp.

• 1971 Intel introduced the 8080 1st uP.
• 1976 Intel introduced the 8748 uC.
• 1980 Intel introduced the 8051 - The first in the
  MCS-51 line.
• 4K Bytes ROM
• 128 Bytes RAM
• 32 I/O lines
• 2 16-bit timers.
• The 8051 is well established and new variations
  of the 8051 continue to be developed.

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Microprocessor Based Computers

• A CPU with external RAM, ROM, and devices.
• Address, data and control buses are used for data
  transfer.
• Microprocessors are fairly useless without being
  combined with numerous other components.

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Microprocesor Based Computers
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The Central Processing Unit

• CPU performs 2 operations
• Fetching an instruction from memory
• Executing an instruction
• Instructions
• Binary codes representing a specific operation.
• Math Add, subtract
• Logical AND, OR
• Data Movement
• A collection of instructions is called an
  Instruction Set. Unique instruction sets are
  designed for the CPU.

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The Central Processing Unit

• Contents of the CPU
• Registers Store information and set operational
  parameters.
• Arithmetic Unit (ALU) Perform operations on
  registers.
• Instruction Decode and Control Unit Determines
  operations to perform and set in motion necessary
  actions.
• Program Counter Holds the memory address of the
  NEXT instruction to be processed.

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The Central Processing Unit
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Fetch Cycle

• Program Counter (PC) placed on address bus.
• Read is activated and data placed on bus.
• Data (instruction- Opcode) is latched in the
  Instruction Register (IR).
• Program Counter is incremented to next memory
  location.

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Fetch Cycle
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Executing an Instruction

• Executing involves the Decode and Control Unit
• Decoding or deciphering the opcode.
• Generating control signals to gate internal
  register in and out of the ALU.
• Signal the ALU to perform specific operations.
• Instructions can be simple or complex requiring
  additional data fetches.
• A series of instructions defines the operation of
  the system software.

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Microcontrollers

• Differ from microprocessors in
• Hardware Architecture
• Applications
• Instruction Set Features

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Hardware

• A uP is a single-chip CPU.
• A uC is a chip which contains
• CPU, RAM, ROM
• Serial Interface
• Timers
• Interrupt System
• RAM is only a fraction of that found on uP
  systems, but sufficient for most intended tasks.
• Interrupts allow fast switching between tasks
  based on events which occur.

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Microcontrollers
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Microcontroller Applications

• Microcontrollers are well suited for systems that
  require a small component count.
• Applications are relatively small and suited to
  very precise tasks.
• Relatively simple I/O control.

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uP vs uC Instruction Set Summary

• uPs
• Are processing intensive work with large
  quantities of data.
• Instruction sets are tailored to nibble, byte,
  word and double word manipulation.
• Addressing provides access to large arrays of
  data.
• uCs
• Instruction Set catered to I/O, including bit
  manipulation set, clear, logical operations.
• Instructions are compact, many 1 byte.

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Memory Comparisons

• Computer have a large RAM to ROM ratio for O/S,
  applications and data.
• uCs have a large ROM to RAM ratio since programs
  are stored on ROM and very little data storage is
  typical.

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Overview of the 8051 Family

• One of the oldest (Intel MCS-51 in 1980) and
  probably the most popular microcontroller. Many
  derivatives are marketed by a number of vendors.
• Common features,
• 8-bit processor
• 4 I/O ports each 8bits wide
• max of 64K on-chip ROM (usually 0k to 4k)
• max of 64K external data memory
• max of 64K external code memory
• 2 timers, one serial port
• 128 bytes of on-chip RAM
• various speeds from 12MHz
• Clones may have different on-chip memory, timers

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The 8051 Family
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8051 Architecture
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The 8051 Microcontroller
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8051 Pinout

• Port 0
• General purpose I/O
• For external memory Multiplexed Address/Data
  bus.
• Port 1
• General purpose I/O.
• Port 2
• General purpose I/O
• For external memory High-Order Address
• Port 3
• General Purpose I/O
• Alternative function pins.

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8051 Pinout

• P3 is shared with control lines
• Serial I/O RxD, TxD,
• external interrupts INT0,INT1
• Counter control T0, T1

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8051 Pinout

• External device interfacing
• EA - External Access (L for ext Memory)
• ALE - Address Latch Enable
• PSEN Program Store Enable
• WR Write Enable
• RD Read Enable

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8051 Pinout

• PSEN Program Store Enable
• Output signal on pin 29.
• Used to enable external code memory when
  accessing external ROM.
• Low to enable OE on external ROM.
• ALE Address Latch Enable (pin 30)
• Used to latch the low order address byte on port
  0 when accessing external memory RAM or ROM.
• Pulses 1/6th of the oscillator clock.

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8051 Pinout

• EA External Access
• When tied HIGH, Memory 0 4K code memory is
  accessed from internal ROM.
• When tied LOW, external memory is used for all
  code access.
• Must be tied low for the 8031/32.
• Used for programming voltage (21V) on EPROM
  version of the 8051.

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8051 Pinout

• RST Reset
• HIGH for 2 clock cycles resets registers and
  program counter (to 0000h) for an orderly
  startup.

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8051 Pinout

• XTAL1, XTAL2 Oscillator inputs.
• 12MHz typically for the 8051.
• Class use 11.059Mhz.
• Power 5V for Vcc and 0V Ground.

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Memory Organization

• Separate memory for code and data.
• Internal (4K) and/or external (64K) ROM for code.
• On-chip RAM
• General purpose storage
• Bit-addressable storage
• Register banks
• Special Function Registers (SFRs)
• I/O ports are memory mapped directly to SFR RAM
  locations.
• Stack resides within internal RAM.

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8031 Memory Space
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General Purpose RAM

• RAM byte locations 00-7FH may be used as general
  purpose for the user
• 00-2FH are also Register Banks used by many
  instructions.
• The Stack is also maintained in this block of
  memory.Data may be copied into or from an
  addressMOV 20H, 10HMOV A,20H

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General Purpose RAM

• Bit Addressable RAM
• There are 210 bit-addressable RAM locations for
  bit storage and manipulation. Many of these
  reside in the SFR area for bit-control of the
  registers.
• Bits may set or clearedSETB 90HCLR 90H

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General Purpose RAM
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Direct and Indirect Addressing
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Direct Addressing of the Special Function
Register (SFR)
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Register Banks

• RAM locations 00 to 1FH (32 bytes) are 4 Register
  banks, each with 8 bytes named R0-R7.
• An instruction using a register bank may be
  performed with less code and faster than other
  instructions (1 byte vice 2).MOV R0,A
• R0 implies 1 of 4 bytes dependent on which bank
  is selected. This allows different section of
  programs to use the register banks for their own
  purposes without conflict.

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Special Function Registers (SFRs)

• Internal registers are made part of RAM for
  direct access and bit manipulation.
• These registers are manipulated either through
  through the instruction set or directly for
  processor control.

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SFRs
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Special Function Registers (SFRs)

• Accumulator (Acc or A)
• Primary register for byte operations such as math
  and logical operations.
• B Register (B)
• Used along with the Accumulator for
  multiplication/division.
• These are 16-bit results, A is the low byte, B
  the high byte.

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Special Function Registers (SFRs)

• Program Status Word (PSW)

• CY Carry Flag Set on addition carry or
  borrow Bit Boolean Accumulator
• AC Aux Carry Flag Set if add result is NOT BCD.
• FO Flag 0 User general purpose.
• RS1 RS0 Reg. Bank Select 2 bits to select Reg.
  Banks 0-3.
• OV Overflow Flag For signed arithmetic when
• 127 or -128 is exceeded.
• P Parity After each machine instruction, the
• parity bit is updated for even-parity
• the accumulator.

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Special Function Registers (SFRs)

• Stack Pointer (SP)
• Points to the address of top of the stack.
• Addresses and data are pushed onto the stack
  and popped off, last-in, first-out (LIFO).
• The stack is incremented prior to pushing.
• The reset value of SP is 07F which would over-run
  the register bank area. (its incremented before
  use to 08H)
• If the SP is not reinitialized register banks 1
  (maybe 2 and 3) might not be available for use.

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Special Function Registers (SFRs)

• Data Pointer (DPTR)
• 16-bit register used to address external RAM.
• The 16-bit address is place on Ports 0 and 2.
• RD and WR I/Os are used to determine data
  direction.
• Data is moved on Port 0

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Special Function Registers (SFRs)

• Port Registers
• All port registers are directly byte and bit
  addressable.
• Configuration of external memory may limit use of
  these ports 0,2 and 3 for general use.

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Special Function Registers (SFRs)

• Timer Registers
• Two 16-bit registers are used for timers or
  counters.
• Other applicable registers for these operations
  are TCON and TMOD

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Special Function Registers (SFRs)

• Serial Port Registers
• Serial data can be transmitted to and received
  from devices such as modems, computers, serial
  A/Ds, etc.
• One register, SBUF holds outgoing and incoming
  data.
• SCON is used to control serial operations.

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Special Function Registers (SFRs)

• Interrupt Registers
• The 8051 has a 5-source, 2-priority interrupt
  structure.
• External Interrupts (2)
• Counters/Timers (2)
• Serial
• Set using the IE and IP registers.

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Power Control Register (PCON)

• IDL Idle mode. Set to activate idle mode, only
  exit is an interrupt or reset.
• PD Power down. Only exit is a reset.
• GF0,GF1 General purpose
• 4,5,6 Undefined
• SMOD Serial Mode BAUD selector.

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External Memory

• Useful when expanded ROM, RAM or I/O must be
  used.
• Can address up to 64K of external memory.
• Port 0 is multiplexed for both address (Low byte)
  and memory.
• Port 2 is High Address Bus.
• ALE, PSEN, RD,WR are used for control.

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External ROM

• Address is placed on Port 0 and 2.
• ALE goes high to latch in the Low Address from
  port 0.
• Port PSEN goes low to allow enable output from
  EPROM memory.
• Port 0 reads the instruction from EPROM

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External ROM
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External ROM
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External ROM
ALE
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External RAM

• External RAM memory location can be accessed
  using MOVX instruction
• The DPTR register for 64K access.
• Using RO or R1 for 256 byte access Frees Port 2
  for other uses.

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External RAM

• Address is placed on Port 0 (and port 2).
• ALE latches in low address.
• For writing
• Data is placed on Port 0
• WR goes to write to RAM
• For reading
• RD goes low to enable RAM output.
• Port 0 Reads data.

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External RAM
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External RAM