Introduction to CMOS VLSI Design Lecture 4: DC

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Introduction toCMOS VLSIDesignLecture 4 DC
Transient Response

• David Harris
• Harvey Mudd College
• Spring 2004

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Outline

• DC Response
• Logic Levels and Noise Margins
• Transient Response
• Delay Estimation

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Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

4
Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

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DC Response

• DC Response Vout vs. Vin for a gate
• Ex Inverter
• When Vin 0 -gt Vout VDD
• When Vin VDD -gt Vout 0
• In between, Vout depends on
• transistor size and current
• By KCL, must settle such that
• Idsn Idsp
• We could solve equations
• But graphical solution gives more insight

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Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vgsn gt Vdsn lt Vgsn gt Vdsn gt
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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vgsn gt Vtn Vdsn lt Vgsn Vtn Vgsn gt Vtn Vdsn gt Vgsn Vtn
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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vgsn gt Vtn Vdsn lt Vgsn Vtn Vgsn gt Vtn Vdsn gt Vgsn Vtn
Vgsn Vin Vdsn Vout
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nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vin lt Vtn Vgsn gt Vtn Vin gt Vtn Vdsn lt Vgsn Vtn Vout lt Vin - Vtn Vgsn gt Vtn Vin gt Vtn Vdsn gt Vgsn Vtn Vout gt Vin - Vtn
Vgsn Vin Vdsn Vout
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vgsp lt Vdsp gt Vgsp lt Vdsp lt
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vgsp lt Vtp Vdsp gt Vgsp Vtp Vgsp lt Vtp Vdsp lt Vgsp Vtp
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vgsp lt Vtp Vdsp gt Vgsp Vtp Vgsp lt Vtp Vdsp lt Vgsp Vtp
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vin gt VDD Vtp Vgsp lt Vtp Vin lt VDD Vtp Vdsp gt Vgsp Vtp Vout gt Vin - Vtp Vgsp lt Vtp Vin lt VDD Vtp Vdsp lt Vgsp Vtp Vout lt Vin - Vtp
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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I-V Characteristics

• Make pMOS is wider than nMOS such that bn bp

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Current vs. Vout, Vin
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Load Line Analysis

• For a given Vin
• Plot Idsn, Idsp vs. Vout
• Vout must be where currents are equal in

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Load Line Analysis

• Vin 0

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Load Line Analysis

• Vin 0.2VDD

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Load Line Analysis

• Vin 0.4VDD

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Load Line Analysis

• Vin 0.6VDD

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Load Line Analysis

• Vin 0.8VDD

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Load Line Analysis

• Vin VDD

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Load Line Summary
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DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

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Operating Regions

• Revisit transistor operating regions

Region nMOS pMOS
A
B
C
D
E
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Operating Regions

• Revisit transistor operating regions

Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
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Beta Ratio

• If bp / bn ? 1, switching point will move from
  VDD/2
• Called skewed gate
• Other gates collapse into equivalent inverter

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Noise Margins

• How much noise can a gate input see before it
  does not recognize the input?

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Logic Levels

• Logic levels are defined at unity gain point of
  DC transfer characteristic to give conservative
  bound on worst case static noise margin

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Noise Margins (cont)

• Noise margins values specified in CMOS datasheets
  for IOs. From Texas Instruments OMAP CPU
  (Vdd1.8V)
• VIL 0.35Vdd (max), VIH 0.65Vdd (min)
• VOL 0.2 (max), VOH Vdd 0.2 (min)
• Noise margin Low (NML), Vdd 1.8 V
• NML VIL VOL
• NML 0.351.8 0.2 0.63 0.2 0.43V
• Noise margin high (NMH), Vdd 1.8 V V
• NMH VOH VIH
• NMH (1.8 0.2) (0.651.8) 1.6 -1.17
  0.43V

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Transient Response

• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t)
  changes
• Requires solving differential equations
• Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Delay Definitions

• tpdr
• tpdf
• tpd
• tr
• tf fall time

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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time (aka, transistion time)
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall time (aka, transistion time)
• From output crossing 0.8 VDD to 0.2 VDD

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Delay Definitions

• tcdr rising contamination delay
• From input to rising output crossing VDD/2
• this is a MINIMUM time
• tcdf falling contamination delay
• From input to falling output crossing VDD/2
• this is a MINIMUM time
• tcd average contamination delay
• tpd (tcdr tcdf)/2

Contamination delays used for race conditions.
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Trigger Point

• VDD/2 is the trigger point for delay measurement
• Prop delay measured from 50 Vin to 50 Vout
• Can also choose different points
• 40/60 points
• inverting TPHL - 40 Vin to 60 Vout
• noninverting TPHL 60 Vin to 60 Vout
• 30/70 points
• inverting TPHL - 30 Vin to 70 Vout
• noninverting TPHL 70 Vin to 70 Vout
• Advantage of 50 is that definition is same for
  inverting/non-inverting delays. Disadvantage is
  that for long transition times, the 50 trigger
  point can yield negative delays.
• Just be consistent in how delay is measured.

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Simulated Inverter Delay

• Solving differential equations by hand is too
  hard
• SPICE simulator solves the equations numerically
• Uses more accurate I-V models too!
• But simulations take time to write

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Delay Estimation

• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask What if?
• The step response usually looks like a 1st order
  RC response with a decaying exponential.
• Use RC delay models to estimate delay
• C total capacitance on output node
• Use effective resistance R
• So that tpd RC
• Characterize transistors by finding their
  effective R
• Depends on average current as gate switches

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RC Delay Models

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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Elmore Delay

• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

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Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Delay Components

• Delay has two parts
• Parasitic delay
• 6 or 7 RC
• Independent of load
• Effort delay
• 4h RC
• Proportional to load capacitance

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Contamination Delay

• Best-case (contamination) delay can be
  substantially less than propagation delay.
• Ex If both inputs fall simultaneously

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Diffusion Capacitance

• we assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too

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Layout Comparison

• Which layout is better?