Timing Analysis of Cyclic Combinational Circuits

1
Timing Analysis of Cyclic Combinational
Circuits
Marc D. Riedel and Jehoshua Bruck
California Institute of Technology
Marrella splendens
Cyclic circuit
IWLS, Temecula Creek, CA, June 4, 2004
2
Combinational Circuits
The current outputs depend only on the current
inputs.
3
Combinational Circuits
Generally acyclic (i.e., feed-forward) structures.
4
Cyclic Combinational Circuits
An acyclic circuit computing these functions
requires 8 gates.
x
a
b
x
c
d
5
Timing Analysis
Predicated on a topological ordering.
l1 1
l4 3
l3 2
l2 1
l5 2
6
Timing Analysis
Predicated on a topological ordering.
l1 1
10
l4 3
x
11
12
c
l3 2
10
y
g1
10
z
g4
02
l2 1
x
10
g3
l5 2
10
z
01
10
y
g2
12
s
g5
(assume a delay bound of 1 time unit for each
gate)
7
Cyclic Combinational Circuits
No topological ordering.
x
How can we perform timing analysis?
AND
a
OR
b
AND
x
OR
c
AND
d
OR
8
Cyclic Combinational Circuits
No topological ordering.
14
10
x
How can we perform timing analysis?
AND
15
00
a
OR
16
10
b
AND
11
10
x
OR
12
10
c
AND
13
00
d
OR
9
Prior Work
In previous papers, we presented

• Algorithms for functional analysis (IWLS03)
• Strategies for synthesis (DAC03).

In trials on benchmark circuits, cyclic
optimizations reduced the area of by as much as
30
10
Optimization for Area
application of script.rugged and mapping
Benchmark Berkeley SIS Caltech CYCLIFY Improvement
5xp1 203 182 10.34
ex6 194 152 21.65
planet 943 889 5.73
s386 231 222 3.90
bw 302 255 15.56
cse 344 329 4.36
pma 409 393 3.91
s510 514 483 6.03
duke2 847 673 20.54
styr 858 758 11.66
s1488 1084 1003 7.47
Number of NAND2/NOR2 gates in Berkeley SIS vs.
CYCLIFYsolutions
11
Contributions
In this paper, we discuss

• An algorithm for timing analysis.
• Synthesis results, with optimization jointly
  targetingarea and delay.

In trials on benchmarks circuits, cyclic
optimizations simultaneously reduced the area by
up to 10 and thedelay by up to 25.
12
Related Work
Malik (1994), Hsu, Sun and Du (1998), and Edwards
(2003) considered analysis techniques for cyclic
circuits.
Their approach identify equivalent acyclic
circuits.
acyclic circuit
cyclic circuit
Unravelling cyclic circuits this way is a
difficult task.
13
Our Approach
Perform event propagation, directly on a cyclic
circuit.
10
00
16
10
13
10
00
14
Our Approach
Perform event propagation, directly on a cyclic
circuit.
Compute events symbolically, with BDDs.
x0
a0
f1b(ax(cd))6
cyclic circuit
b0
f2dc(xba))6
c0
d0
15
Circuit Model
Perform static analysis in the floating-mode.
At the outset
a controlling input
full set ofnon-controlling inputs
unknown/undefinedoutput
16
Circuit Model
Perform static analysis in the floating-mode.
At the outset
During the analysis, only signals driven
(directly or indirectly) by the primary inputs
are assigned definite values.
17
Circuit Model
Up-bounded inertial delay model.
Ensures monotone speed-up property.
each gate has delay in 0, td
18
Circuit Model
The arrival time at a gate output is determined

• either by the earliest controlling input.

02
13
03
06
(assuming a delay bound of 1)
19
Circuit Model
The arrival time at a gate output is determined

• either by the earliest controlling input

• or by the latest non-controlling input.

12
13
17
16
(assuming a delay bound of 1)
20
Timing Analysis
Characterize arrival times symbolically (with
BDDs)
set of input assignments that produce 0
set of input assignments that produce 1
Implicitly
21
Timing Analysis
Characterize arrival times symbolically (with
BDDs)
set of input assignments that produce 0
set of input assignments that produce 1
Time-stamp the characteristic sets
22
Initialization
internal signals
primary inputs
x
23
Propagation
If there is a change in the characteristic set of
a gates fan-in
For a controlling input value v, producing an
output value w,
24
Propagation
If there is a change in the characteristic set of
a gates fan-in
For non-controlling input values v1, v2, v3
producing an output value w,
25
Propagation
If there is a change in the characteristic set of
a gates fan-in
delay in 0, td
26
Example
0
time 1
time 2
time 3
time 4
time 5
time 6
0
AND
0
x
OR
0
0
a
AND
0
b
0
OR
0
x
0
AND
0
c
OR
0
0
d
27
Timing Analysis
28
Multi-Terminal BDDs
For finer-grained timing information,preserve a
history of the changes.
Reference Bahar et al., Timing Analysis using
ADDs"
29
Synthesis
N1
N2
N3
Select best solution through a branch-and-bound
search.
N4
N6
Analysis algorithm is used to validate and rank
potential solutions.
N7
N5
N8
N9
See The Synthesis of Cyclic Combinational
Circuits, DAC03.
30
Implementation CYCLIFY Program

• Incorporated synthesis methodology in a general
  logic synthesis environment (Berkeley SIS
  package).
• Trials on wide range of circuits
• randomly generated
• benchmarks
• industrial designs.
• Conclusion nearly all circuits of practical
  interest can be optimized with feedback.

31
Optimization for Area and Delay
application of script.delay and mapping
Berkeley SIS Berkeley SIS Caltech CYCLIFY Caltech CYCLIFY Caltech CYCLIFY Caltech CYCLIFY
benchmark Area Delay Area Improvement Delay Improvement
p82 175 19 167 4.57 15 21.05
t1 343 17 327 4.66 14 17.65
in3 599 40 593 1.00 33 17.50
in2 590 34 558 5.42 29 14.71
5xp1 210 23 180 14.29 22 4.35
bw 280 28 254 9.29 20 28.57
s510 452 28 444 1.77 24 14.29
s1 566 36 542 4.24 31 13.89
duke2 742 38 716 3.50 34 10.53
s1488 1016 43 995 2.07 34 20.93
s1494 1090 46 1079 1.01 39 15.22
Area and Delay of Berkeley SIS vs.
CYCLIFYsolutions.
Area number of NAND2/NOR2 gates. Delay 1 time
unit/gate.
32
Discussion
Analysis through symbolic event propagation

• Existing methods can be applied to cyclic
  circuits.
• Complexity is comparable for cyclic and acyclic
  circuits.

Synthesis strategies targeting area and delay

• Nearly all circuits can be optimized with
  cycles.
• Optimizations are significant.

33
Future Directions

• Apply more realistic timing models for analysis.
• Use more efficient symbolic techniques (e.g., use
  boolean satisfiability (SAT)-based techniques).
• Incorporate more sophisticated search heuristics
  into synthesis.