ABC: A System for Sequential Synthesis and Verification

1
ABC A System for Sequential Synthesis and
Verification

• Berkeley
• Logic Synthesis and Verification
• Group

Robert Brayton Alan Mishchenko
2
Overview

• Introduction
• What and why ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes

3
A Plethora of ABCs

• http//en.wikipedia.org/wiki/Abc
• ABC (American Broadcasting Company)
• A television network
• ABC (Active Body Control)
• ABC is designed to minimize body roll in corner,
  accelerating, and braking. The system uses 13
  sensors which monitor body movement to supply the
  computer with information every 10 ms
• ABC (Abstract Base Class)
• In C, these are generic classes at the base of
  the inheritance tree objects of such abstract
  classes cannot be created
• ABC (supposed to mean as simple as ABC)
• A system for sequential synthesis and
  verification at Berkeley

4
Why We Decided to Build ABC

• SIS
• Outdated, but many research papers on how a new
  algorithm beats SIS results
• Not supported
• MVSIS
• Gave us a reason to work on logic synthesis
• Learned a lot about new methods and better data
  structures
• Could see how specializing to binary could
  provide substantial improvements.
• ABC
• Initial intention was to re-implement all
  algorithms using new data structures (daunting
  task)
• Discovered rewriting AIGs
• P. Bjesse and A. Boralv, "DAG-aware circuit
  compression for formal verification", Proc. ICCAD
  04, pp. 42-49.
• Decided to try to keep all transformations fast
  and scalable
• No BDDs
• No SOPs
• No Espresso

5
What Is Berkeley ABC?

• A system for logic synthesis and verification
• Fast
• Scalable
• High quality results (industrial strength)
• Exploits synergy between synthesis and
  verification
• A programming environment
• Open-source
• Evolving and improving over time

6
Design Flow
Verification
System Specification
RTL
ABC
Logic synthesis
Technology mapping
Physical synthesis
Manufacturing
7
Screenshot
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Areas Addressed by ABC

• Combinational synthesis
• AIG rewriting
• technology mapping
• resynthesis after mapping

• Sequential synthesis
• retiming
• structural register sweep
• merging seq. equiv. nodes

• Formal verification
• combinational equivalence checking
• bounded sequential verification
• unbounded sequential verification
• equivalence checking using synthesis history

9
Combinational Synthesis

• AIG rewriting minimizes the number of AIG nodes
  without increasing the number of AIG levels

Rewriting AIG subgraphs

• Pre-computing AIG subgraphs
• Consider function f abc

Rewriting node A
?
Rewriting node B
?
In both cases 1 node is saved
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Technology Mapping
Input A Boolean network (And-Inverter Graph)
Output A netlist of K-LUTs implementing AIG and
optimizing some cost function
Technology Mapping
The subject graph
The mapped netlist
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Sequential Synthesis

• Structural register sweep (scleanup)
• Merge registers with identical drivers
• Replace stuck-at registers by constants
• Retiming (dretime)
• Minimize the number of registers under delay
  constraints
• Preserves equivalent initial state
• Sequential SAT sweeping (scorr)
• Detecting and merging sequencially equivalent
  nodes

12
Formal Verification

• Equivalence checking
• Takes two designs and makes a miter (AIG)
• Model checking safety properties
• Takes design and property and makes a miter (AIG)
• The goals are the same to transform AIG until
  the output is proved constant 0
• Breaking News ABC won a model checking
  competition at CAV in August 2008

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Model Checking Competition
14
(No Transcript)
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5. ABC 238
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Time (sec)
ABC
problems solved
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Command dprove in ABC

• transforming initial state (undc, zero)
• converting into an AIG (strash)
• creating sequential miter (miter -c)
• combinational equivalence checking (iprove)
• bounded model checking (bmc)
• sequential sweep (scl)
• phase-abstraction (phase)
• most forward retiming (dret -f)
• partitioned register correspondence (lcorr)
• min-register retiming (dretime)
• combinational SAT sweeping (fraig)
• for ( K 1 K ? 16 K K 2 )
• signal correspondence (scorr)
• stronger AIG rewriting (dc2)
• min-register retiming (dretime)
• sequential AIG simulation
• interpolation (int)
• BDD-based reachability (reach)
• saving reduced hard miter (write_aiger)

Preprocessors
Combinational solver
Fast engines
Medium engines
Slower Main induction loop
Last-gasp engines
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ABC vs. Other Tools

• Industrial
• well documented, fewer bugs
• - black-box, push-button, no source code, often
  expensive
• SIS
• traditionally very popular
• - data structures / algorithms outdated, weak
  sequential synthesis
• VIS
• very good implementation of BDD-based
  verification algorithms
• - not meant for logic synthesis, does not feature
  the latest SAT-based implementations
• MVSIS
• allows for multi-valued and finite-automata
  manipulation
• - not meant for binary synthesis, lacking recent
  implementations

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How Is ABC Different From SIS?
Equivalent AIG in ABC
AIG is a Boolean network of 2-input AND nodes and
invertors (dotted lines)
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One AIG Node Many Cuts
Combinational AIG

• Manipulating AIGs in ABC
• Each node in an AIG has many cuts
• Each cut is a different SIS node
• No a priori fixed boundaries
• Implies that AIG manipulation with cuts is
  equivalent to working on many Boolean networks at
  the same time

f
a
c
d
e
b
Different cuts for the same node
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Comparison of Two Syntheses

• Classical synthesis
• Boolean network
• Network manipulation (algebraic)
• Elimination
• Factoring/Decomposition
• Speedup
• Node minimization
• Espresso
• Dont cares computed using BDDs
• Resubstitution
• Technology mapping
• Tree based

• ABC contemporary synthesis
• AIG network
• DAG-aware AIG rewriting (Boolean)
• Several related algorithms
• Rewriting
• Refactoring
• Balancing
• Speedup
• Node minimization
• Boolean decomposition
• Dont cares computed using simulation and SAT
• Resubstitution with dont cares
• Technology mapping
• Cut based with choice nodes

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Existing Capabilities (2005-2008)
ABC
23
Overview

• Introduction
• What is ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes
• Summary

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Command speedup

• Timing Criticality
• Critical nodes
• Used by many traditional algorithms
• Critical edges
• Used by our algorithm
• We pre-compute critical edges of critical nodes
• Reduces computation
• An edge between critical nodes may not be
  critical
• See illustration edge 1?3

Primary outputs
4
4
3
3
2
2
1
1
Primary inputs
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Delay-Oriented Restructuring

• Using traditional MUX-restructuring
• AKA generalized select transform

x and y are the critical edge inputs
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Overall Algorithm

• mapped netlist performSpeedup (
• subject graph S, // S is an And-Inverter
  Graph
• mapped netlist M, // M was previously
  derived by tech-mapping of S
• timing window w, // w is used to detect the
  critical paths
• logic depth l, // l is used to
  detect a logic cone rooted at a node
• edge count p ) // p limits the number
  critical edges of the cone
• perform timing analysis of M with unit-delay
  or LUT-library model
• pre-compute critical section of M as nodes n
  such that 0 ? slack(n) ? w
• pre-compute timing-critical edges connecting
  these nodes
• for each timing critical node n
• find cone C of M that extends l
  levels down from n
• pick the set of timing-critical
  edges V feeding into C
• if the number of edges in V exceeds
  p, continue
• find logic cone C in S
  corresponding to C in M
• find variables V in S corresponding
  to V in M
• derive cofactors of the function of
  C w.r.t. variables in V
• build multiplexer tree C of the
  cofactors using variables in V
• add structural choice C C to the
  subject graph S

Done only once
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Experimental Results for speedup
Time1 the runtime of AIG restructuring
only Time2 the total runtime of Speedup Geomean
geometric averages of columns Ratios ratios
of geometric averages
LUT number of LUTs Lev number of LUT
levels Delay delay using LUT library Total
total runtime of Baseline
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Overview

• Introduction
• What is ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes
• Summary

29
Basic Inner Core Algorithm (DSD)

• We use a fast disjoint support decomposition
  (DSD) algorithm as our underlying subroutine
• follows Bertacco and Damiani, "The disjunctive
  decomposition of logic functions, ICCAD '97
• but
• uses heuristics to speed it up
• no BDDs
• uses truth tables
• limit inputs to up to 16

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Disjoint Support Decomposition (DSD) (Simple
Disjunctive Decomposition)

• Theorem 1 Ashenhurst 1959. For a completely
  specified Boolean function, there is a unique
  maximal DSD (up to the complementation of inputs
  and outputs and factoring of ANDs/ORs and XORs).

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Non-Disjoint Decomposition

• Definition A function F has an ( )
  -decomposition if it can be written as
• where ( ) is a partition of the
  variables x and D is a single output function.

The variables in the set b are called the shared
variables. The variables a are called the bound
set and c the free set.
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Non-Disjoint Decomposition

• Theorem 2 A function has an
  - decomposition if and only if each of the
  cofactors of F with respect to has a DSD
  structure in which the variables are in a
  separate sub-tree.

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Application of Factoring(uses Theorem 2)

• Rewriting a k-LUT mapped circuit.
• For each LUT, and each cut of no more than 16
  inputs,
• express the output of the LUT as truth table in
  terms of the cut variables F(x)
• Find variables b such that its cofactors are
  support reducing
• we exhaustively look for up to two variables in
  the b set
• Take the best (a,b) set and decompose
  FH(D(a,b),b,c)
• Recursively decompose H and D if they do not fit
  into a k-LUT.
• If improvement, replace LUTs in cut with its new
  decomposition.

Experimental results later
34
Overview

• Introduction
• What is ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes
• Summary

35
Windowing a Node in the Networkfor Dont-Care
Computation
Boolean network (k-LUT mapped circuit)

• Definition
• A window for a node in the network is the context
  in which the dont-cares are computed
• A window includes
• n levels of the TFI
• m levels of the TFO
• all re-convergent paths captured in this scope
• Window with its PIs and POs can be considered as
  a separate network

36
Care Set Representation
Miter constructed for the window POs
If output is 1 then we care

Window
Window
Same window with inverter
f
f
Window
x
x
s
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Resubstitution

• Resubstitution considers a node in a Boolean
  network and expresses it using a different set of
  fanins

X
X
Computation can be enhanced by use of dont cares
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Resubstitution with Dont-Cares

• Consider all or some nodes in Boolean network.
• For each node
• Create window
• Select possible fanin nodes (divisors)
• For each candidate subset of divisors
• Rule out some subsets using simulation
• Check resubstitution feasibility using SAT
• Compute resubstitution function using
  interpolation
• A low-cost by-product of completed SAT proofs
• Update the network if there is an improvement

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Resubstitution with Dont Cares

• Given
• node function F(x) to be replaced
• care set C(x) for the node
• candidate set of divisors gi(x) for
  re-expressing F(x)
• Find
• A resubstitution function h(y) such that F(x)
  h(g(x)) on the care set
• SPFD Theorem Function h exists if and only if
  every pair of care minterms, x1 and x2,
  distinguished by F(x), is also distinguished by
  gi(x) for some i

40
Checking Resubstitution using SAT
SPFD theorem in practice

1. Note use of care set, C.
2. Resubstitution function exists if and only if SAT
   problem is unsatisfiable.
3. An h(g) is obtained by interpolation

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Experimental Results
42
Overview

• Introduction
• What is ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes
• Summary

43
The Main Idea

• Consider registers and nodes of a design
• Detect candidate equivalences in this set using
  random/guided simulation
• Prove candidates by K-step induction
• Merge the resulting equivalences
• This is a subset of sequential synthesis with
• Practical advantages (does not move registers,
  etc)
• Scales to large designs
• Offers substantial improvements
• Comes with a verification guarantee

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Base Case Inductive Case
?
Candidate equivalences A,B, C,D
?
Proving internal equivalences in a topological
order in frame K
?
?
PIk
0
0
PI1
C
?
D
A
Assuming internal equivalences to in
uninitialized frames 0 through K-1
?
B
PI1
0
0
PI0
C
D
Initial state
A
B
Proving internal equivalences in initialized
frames 0 through K-1
PI0
Symbolic state
45
Dynamic Partitioning (register correspondence)
Illustration for two candidate equiv. classes
A,B, C,D
Partition 1
Partition 2
46
Academic Benchmarks
Columns Baseline, Reg Corr and Sig Corr
show geometric means.
47
Industrial Benchmarks
In case of multiple clock domains, optimization
was applied only to the domain with the largest
number of registers.
48
Reasons for Large Improvements

• Redundancy introduced by HDL compilers
• Early logic duplication by the designer
• Accidental sequential redundancies
• Sequential redundancies present due to reuse of
  design components that had more functionality
  than needed

49
Overview

• Introduction
• What is ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes
• Summary

50
Motivation

• Fewer pin-to-pin connections should make the
  design easier to place and route
• Newer FPGAs allow two outputs per LUT
• Thus fewer pin-to-pin connections should produce
  a mapping that packs better into dual-output
  LUTs

51
Area Recovery Overview

• Perform delay-optimal mapping
• Recover area off critical paths
• Area-flow (global view)
• Chooses cuts with better logic sharing
• Exact local area (local view)
• New idea Cut-based area recovery algorithms can
  be extended to minimize edges (pin-to-pin
  connections)

Both are important
52
WireMap Algorithm

• Perform delay-optimal mapping
• Recover area off critical paths
• Area-flow (global view)
• Break ties with minimum edge flow
• Exact local area (local view)
• Break ties with exact local edge count

53
Experimental Setup

• WireMap implemented in ABC
• Compared WireMap against two algorithms in ABC
• Baseline basic mapping with area recovery
• Mapping with Structural Choices mapping with
  area recovery for several netlists produced by
  synthesis
• WireMap was implemented on top of mapping with
  choices
• Used VPR to place/route design for wirelength and
  critical path delays
• Used maximum cardinality matching to pack
  single-output LUTs into dual-output LUTs using

54
Results Summary

• Comparing WireMap against the best mapping with
  structural choices in ABC
• WireMap results
• Reduction in edges by 9.3
• Reduction in dual-output LUT count by 9.4,
  compared to mapping with choices
• Single-output LUT count only reduced by 1.3
• Reduction in wire length by 8.5
• Reduction in power by 20

55
Overview

• Introduction
• What is ABC?
• ABC fundamentals
• Areas addressed by ABC
• Synthesis
• Technology mapping
• Verification
• Contrast with classical methods
• How is ABC different from SIS?
• Recent work
• Speedup
• Factoring
• Dont-care based optimization
• Scalable sequential synthesis
• WireMap
• White boxes
• Summary

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Comb and Seq Boxes
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Treating Boxes as Black
For simplicity, boxes can be treated as black.
Thus box outputs become inputs to the rest of the
logic and box inputs become outputs. Delay and
logic information is lost.
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Treating Boxes as White
Example Nodes o1 and o3 may be equivalent in the
design, but this equivalence cannot be detected
if the boxes are treated as black. Solution
Consider logic inside white boxes for synthesis,
but keep it unchanged during synthesis and
mapping.
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Future Work
ABC
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To Learn More

• Visit ABC webpage http//www.eecs.berkeley.edu/al
  anmi/abc
• Read recent papers http//www.eecs.berkeley.edu/a
  lanmi/publications
• Send email
• alanmi_at_eecs.berkeley.edu
• brayton_at_eecs.berkeley.edu