09:00 FOPI electronics: specs and performance M. Ciobanu (GSI) 09:15 FEE for HADES RPC's D. Belvers (Santiago) ... New chip TC3 with lager devices, PMOS pair, ...
Link local track segments into distinct 3D tracks (FPGA logic) ... Software may be in good shape since DDU already supported by EMU in XDAQ environment ...
SR now has 3 memories rather than 6 per stub [total of 45 per board] ... Crossing Analyzer and Ghost Busting [background reduction] to Verilog model. ...