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Zongbin Liu, Lingchen Zhang,

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Efficient Pipelined Stream Cipher ZUC Algorithm in FPGA Zongbin Liu, Lingchen Zhang, Jiwu Jing, Wuqiong Pan * * * * * * frequency. * * * * * * * * * * * * * Outline ... – PowerPoint PPT presentation

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Title: Zongbin Liu, Lingchen Zhang,


1
Efficient Pipelined Stream Cipher ZUC Algorithm
in FPGA
  • Zongbin Liu, Lingchen Zhang,
  • Jiwu Jing, Wuqiong Pan

2
Outline
  • The specification of ZUC Algorithm
  • The pipelined architecture of ZUC in Hardware
  • The Evaluation of the Implementation

3
ZUC Algorithm
  • ZUC is a word-oriented stream cipher, it is
    proposed by Data Assurance and Communication
    Security Research Center (DACAS) of the Chinese
    Academy of Sciences.
  • It takes a 128-bit initial key and a 128-bit
    initial vector as input, and outputs a key stream
    of 32-bit words

4
The architecture of ZUC
5
The architecture of ZUC
  • The linear feedback shift register (LFSR)
  • The Bit-reorganization
  • The nonlinear function F

6
Linear Feedback Shift Register
  • The linear feedback shift register (LFSR) has 16
    of 31-bit registers(s0, s1,, s15).
  • Initialization Stage
  • Working Stage

7
Initialization Stage
u(W?X3)gtgt1
8
Working Stage
9
The Bit-reorganization
10
The nonlinear function F
11
Why hardware implementation?
  • Accelerate Key Generation speed
  • Why can hardware implementation raise the speed.
  • Our Contribution (Aim)
  • Generate 32-bit Key per clock cycle
  • We tested the ZUC on PC( intel 3GHz , 4 cores )
  • The Key generation speed is 400Mbs
  • Our pipelined architecture can research to 7Gbps

12
The difference between Hardware and Software
13
Preparation Work
  • Simple Model of Hardware and Critical Path

14
ZUC Algorithm Critical Path
  • There are five modulo adder in this path

15
Basic Operation in Critical Path in Hardware
  • X Y mod p where p 231 - 1

16
Basic Operation in critical path in hardware
  • For arbitrary integer 0k30, we have
  • 2k X mod p X ltltlt31k
  • Treating X as a 31-bit value, cyclically shifted
    towards the msb by k bit positions
  • In hardware, cyclically shifted needed to change
    the order of the X.

17
Naïve Method 1
18
Naïve Method 2
19
Pipeline architecture
20
Pipelined Architecture
21
The Evaluation Result
22
Snow 3G
  • They use 4 clock to generate one Key
  • Why?

23
(No Transcript)
24
Thanks!
  • Questions?
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