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P1258920007vHOQR
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Noise Canceling in 1-D Data: Presentation #2. Seri Rahayu Abd Rauf. Fatima Boujarwah. Juan Chen. Liyana Mohd Sharipp. Arti Thumar. M2. Jan 24, 2005 ... – PowerPoint PPT presentation
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Title: P1258920007vHOQR
1
Jan 24, 2005 Architecture Proposal
Noise Canceling in 1-D Data Presentation 2
Seri Rahayu Abd Rauf Fatima Boujarwah Juan
Chen Liyana Mohd Sharipp Arti Thumar
M2
Overall Project Objective Implementing Noise
Cancellation Algorithm in Hardware
2
Status
- Design proposal (Done)
- Architecture proposal
- Final algorithm description (Done)
- High level simulation in C (Done)
- Mapping of algorithm into hardware (Done)
- Behavioral Verilog simulation and test bench
(Debugging) - To be done
- Floor plan
- Structural Verilog
- Layout
- Spice simulation
3
Design Decisions
- Use 16-bit floating point numbers approximating
up to 10-5 - Choose M1 because target applications do not
usually have higher harmonics - Change integer multipliers and adders to floating
point - Make a bigger ROM table for the sine and cosine
functions
4
Algorithm Description
- Goal To minimize noise
- Algorithm Based on adaptive filtering depending
on signal weights - Pseudo-code
- Take the input signal and model it using Fourier
Transform - For each sample, model it by approximating the
weight constant and feeding it back to the next
sample - Each sample model is then subtracted from the
original input signal to monitor the error
5
Original Flow-chart
6
Revised Flow-chart
7
The Micron Experiment
8
High Level Simulation in C
Simulation of input before the modification
9
Simulation of input file after the modification
10
Error comparison
11
Mapping of Algorithm into Hardware
- Major functional components
- Floating point multipliers (FPM)
- Floating point adders (FPA)
- 16-bit Registers (Reg)
- ROM sine, cosine
- SRAM µ, µ0, ?0
12
Block Diagram
13
Behavioral Verilog
- always_at_(datum)
- begin
- w10
- w20
- offset 10
- in datum - offset
- sumw0 sumw0 w0
- x1 sin(sumw0)
- x2 cos(sumw0)
- / output truncated Fourier Series/
- out 0
- out w1 x1 w2 x2
- / calculate error/
- e in - out
- /update amplitude weights /
- temp 2mue
14
Revised Transistor Count
Part Transistors
16-bit FPA 5x500 2500
16-bit FPM 5x4000 20000
SRAM 500
ROM 1600
Registers 7x16x14 1568
Total 26168
15
Challenges
- Timing issues
- Need to reuse hardware (multipliers)
- Clock skew
- Pipelined architecture to increase speed and
throughput - SRAM implementation
- ROM implementation
- Transistor count is too high
16
Questions?
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