A Compact Delay Model for SeriesConnected MOSFETs - PowerPoint PPT Presentation

Title: A Compact Delay Model for SeriesConnected MOSFETs


1
A Compact Delay Model for Series-Connected
MOSFETs
Kaveh Shakeri and James D. Meindl
Gigascale Integration Group
April 18, 2002
2
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

3
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

4
A Model for Series-Connected MOSFET is Needed to
Calculate Delay in Most Logic Families
Keeper
z
y
w
x
CLK
z
T4
z
T4
y
T3
y
T3
x
T2
Series-Connected MOSFETs
x
T2
w
T1
w
T1
Dynamic Circuits
Static Circuits
5
A Model for Series-Connected MOSFET is Needed to
Calculate Delay in Most Logic Families
z
w
T9
T7
y
v
x
T10
T6
T8
v
T5
y
w
T2
T4
x
z
T1
T3
- Modeling the worst case delay for complex gates.
- Worst case delay is through series-connected
transistors
6
A New Model is Needed forSeries-Connected
MOSFETs!

• Previous models are not accurate enough!
• A model for SCMS gives an analytic delay
  expression for CMOS gates that enables faster
  simulations than SPICE.
• It gives insight into delay dependence on device
  parameters.
• It also enables us to predict the delay for
  future generations of technology.

SCMS (Series-Connected MOSFETs)
7
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

8
Delay Calculation Using Elmore Model
CL

• Modeling transistors as resistors
• Assuming the drain source capacitors
• are not negligible

• Assuming same size transistors

9
Delay Calculation Using Elmore Model
CL

• Modeling transistors as resistors
• Assuming the drain source capacitors
• are not negligible

• Assuming same size transistors

10
Sakurais Model forSeries-Connected MOSFETs
IDN

• Assuming the drain/source capacitances
• are negligible.

SCMS (Series-Connected MOSFETs)
11
Delay for Different Models
Simulations for the case where drain/source
capacitances are not negligible.
T. Sakurai and A. R. Newton, Delay Analysis of
Series-Connected MOSFET Circuits, IEEE JSSC,
Vol. 26, NO. 2, Feb. 1991.
12
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

13
Best Case Delay
IDN
z
T4
y
T3
x
VDD
T2
Capacitors are discharged
w
T1
- All of the parasitic capacitances are discharged
14
Worst Case Delay
IDN
z
Capacitor charged to VDD-VTH
T4
y
VDD
T3
x
T2
w
T1
- All of the parasitic capacitances are charged
15
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

16
Worst Case Delay for Series-Connected Transistors
Vmax
Voltage
t
T1
T2

• T1 is the delay induced by drain/source
  capacitors and is
• not modeled.
• T2 can be calculated using Sakurais model.

17
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

18
Alpha Power Law model
Saturation region
Linear region

• Empirical MOSFET Model.
• Although this model is very simple it represents
  accurately
• the velocity saturation effect of the
  transistor.
• The physical Alpha-Power Law MOSFET model
  provides a
• physical interpretation of the device
  parameters therefore
• it enables projections for future generations.

Keith Bowman et al. A Physical Alpha-Power Law
MOSFET Model, IEEE JSSC, Oct 1999
19
Modeling Two Series-Connected MOSFETs
M2
M1

• Transistor M2 is operating in the saturation
  region.
• Transistor M1 is operating in the linear
  region.

20
Modeling Series-Connected MOSFETs
IDN
VDD
Saturation
VN-1
VDD

Linear
VDD
VDD
21
Modeling of the Saturated Transistor
IDN
IDN
ID0
IDN
VDD
Vmax
RN
VN-1
Mn
VN-1
VN-1
Vmax
22
Modeling MOSFETs Operating in Linear Region
ID2
ID1
M1,2
M1
V2
V1
ID2
V2
ID1
V1
VDD
VDD
M2
M1
VDD
M1
23
Modeling MOSFETs Operating in Linear Region
ID
ID
ID
R
V
R
VDD
M1
V
M1,2
V
24
Modeling the Transistors as Equivalent Resistors
IDN
CL
IDN
Vmax
RN
CN-1
VN-1
RN-1
CN-2

R2
C1
R1

25
Modeling T1
Vx
Vx
IDN
T1
Vmax
RN
CN-1
Step Response for the worst case delay
VN-1
RN-1
CN-2
t

T1 can be calculated from
R2
C1
R1
V'x is the derivative of Vx with respect to time
26
Calculating T1 from the Transfer Function
Transfer Function
Laplace Transform
27
Calculating T1
For this circuit we have
IDN
Vmax
RN
CN-1
VN-1
RN-1
CN-2

R2
C1
Assuming the transistors have the same size T1
can be simplified to
R1
28
Calculating Delay
V
T2
T1
t
Delay
T1 was modeled T2 can be calculated by Sakurais
model
Delay of series-connected transistor discharging
a capacitor
29
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

30
Verification
0.5?m HP Model

• Less than 9 error using the new model.
• For other models the delay can be up to 50.

31
Delay as a Function of Alpha
Smaller Alpha

• Smaller Alpha results in smaller normalized
  delay

32
Normalized Delay for different Generations of
Technology
FD
N

• Normalized delay is almost constant for
  different
• generations of technology

33
Outline

• Motivation
• Existing Models
• Modeling
• When does the worst case delay happen?
• What are the different components of the delay?
• Modeling the different components of the delay.
• Results
• Conclusion

34
Conclusions

• A new model has been derived for series connected
  MOSFETs.
• The model has less than 9 error compared to the
  SPICE simulation results. Other models the error
  can be up to 50.
• Results show that as alpha is reduced the
  normalized delay of series-connected MOSFETs
  versus number of transistors in series is
  reduced.
• The model shows that normalized delay versus
  number of transistors for different generations
  is constant.