Modular Performance Analysis with RealTime Calculus

1
Modular Performance Analysiswith Real-Time
Calculus
23. November 2005 Workshop on Distributed
Embedded Systems, Leiden, The Netherlands
Lothar Thiele, Simon Künzli, Alex Maxiaguine,
Ernesto Wandeler, et al.
Computer Engineering and Networks Laboratory ETH
Zurich, Switzerland
2
Real-Time Calculus

• Developed at ETH Zurich since 2000
• Based on
• Max-Plus/Min-Plus Algebra Quadrat et al., 1992
• Network Calculus Le Boudec Thiran, 2001

3
Abstract Models for Performance Analysis
Processor
Task
Input Stream
Concrete Instance
Abstract Representation
Service Model
Load Model
Task / Processing Model
4
Load Model
Service Model
Load Model
Processing Model
events
Event Stream
deadline d
t ms
2.5
Arrival Curve a Delay d
au
al
5
Load Model - Examples
Service Model
Load Model
Processing Model
periodic
periodic w/ jitter
periodic w/ burst
complex
6
Service Model
Service Model
Load Model
Processing Model
availability
Resource Availability
t ms
2.5
bu
bl
7
Service Model - Examples
Service Model
Load Model
Processing Model
full resource
bounded delay
TDMA resource
periodic resource
8
Task / Processing Model
Service Model
Load Model
Processing Model
b
a
a
d
b
9
Scheduling / Arbitration
FP
EDF
GPS
TDMA
10
Analysis Delay and Backlog
Service Model
Load Model
Processing Model
bl
bl, bu
au
delay dmax
al, au
al, au
RTC
backlog bmax
bl, bu
11
Case Study
5 Real-Time Input Streams - with jitter - with
bursts - deadline gt period 3 ECUs with own
CCs 12 Tasks 7 Messages - with different
WCED 2 Scheduling Policies - Earliest Deadline
First (ECUs) - Fixed Priority (ECUs
CCs) Hierarchical Scheduling - Static Dynamic
Polling Servers Bus with TDMA - 4 time slots
with different lengths (1,3 for CC1, 2 for
CC3, 4 for CC3)
S1
S2
ECU1
CC1
S3
ECU3
CC3
BUS
S4
ECU2
CC2
S5
Total Utilization - ECU1 59 - ECU2 87 -
ECU3 67 - BUS 56
12
Specification Data
13
The Distributed Embedded System...
ECU1
BUS (TDMA)
CC1
S1
ECU3
CC3
FP
FP
T1.1
FP
FP
S1
PS
C1.1
T1.2
PS
T1.3
T2.1
S2
C1.2
EDF
T3.1
S3
T2.2
C3.2
T3.3
S3
FP
PS
C2.1
T3.2
ECU2
CC2
C3.1
T4.2
FP
T5.2
C4.1
T4.1
S4
C5.1
T5.1
S5
14
... and its Real-Time Calculus Model
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
CC1
S1
T1.1
T1.2
C1.1
C1.2
T1.3
EDF
S2
T2.1
C2.1
T2.2
CC3
PS
S3
T3.1
C3.1
T3.3
T3.2
C3.2
ECU2
CPU
CC2
S4
C4.1
T4.1
T4.2
T5.1
T5.2
S5
C5.1
15
Input Output of Stream 3
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
CC1
S1
T1.1
T1.2
C1.1
C1.2
T1.3
EDF
S2
T2.1
C2.1
T2.2
CC3
PS
S3
T3.1
C3.1
T3.3
T3.2
C3.2
ECU2
CPU
CC2
S4
C4.1
T4.1
T4.2
T5.1
T5.2
S5
C5.1
16
Service Demand Supply for EDF Block
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
CC1
S1
T1.1
T1.2
C1.1
C1.2
T1.3
EDF
S2
T2.1
C2.1
T2.2
CC3
PS
S3
T3.1
C3.1
T3.3
T3.2
C3.2
ECU2
CPU
CC2
S4
C4.1
T4.1
T4.2
T5.1
T5.2
S5
C5.1
17
Service Demand Supply for EDF Block
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
CC1
S1
T1.1
T1.2
C1.1
C1.2
T1.3
EDF
S2
T2.1
C2.1
T2.2
CC3
PS
S3
T3.1
C3.1
T3.3
T3.2
C3.2
ECU2
CPU
CC2
S4
C4.1
T4.1
T4.2
T5.1
T5.2
S5
C5.1
18
Service Demand Supply for EDF Block
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
CC1
S1
T1.1
T1.2
C1.1
C1.2
T1.3
EDF
S2
T2.1
C2.1
T2.2
CC3
PS
S3
T3.1
C3.1
T3.3
T3.2
C3.2
ECU2
CPU
CC2
S4
C4.1
T4.1
T4.2
T5.1
T5.2
S5
C5.1
19
Buffer Requirements
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
3
1.8
1
CC1
S1
T1.1
T1.2
C1.1
3
5
C1.2
T1.3
5
4.1
EDF
S2
T2.1
C2.1
T2.2
CC3
2
4
PS
S3
T3.1
C3.1
5
2
6
T3.3
T3.2
C3.2
ECU2
CPU
1
5
CC2
S4
C4.1
T4.1
T4.2
1.3
4.5
T5.1
T5.2
S5
C5.1
20
Delay Guarantees
BUS
CPU
CPU
ECU1
ECU3
TDMA
PS
PS
CC1
S1
T1.1
T1.2
C1.1
4910
550
2140
C1.2
T1.3
EDF
S2
T2.1
C2.1
T2.2
CC3
PS
S3
T3.1
C3.1
4550
T3.3
T3.2
C3.2
ECU2
CPU
87
303
CC2
S4
C4.1
T4.1
T4.2
329
125
T5.1
T5.2
S5
C5.1
21
System Analysis Time

• Pentium Mobile 1.6GHz
• Matlab 7
• RTC Kernel Prototype (Java 1.4)

22
Tool Support

• Matlab Toolbox for Real-Time Calculus
• Version 1.0 to be released December 2005
• Simulink Frontend
• Prototype under development

23
Limitations of Real-Time Calculus

• High Level of Abstraction
• Time-Interval Domain

24
Thank you!
Ernesto Wandeler wandeler_at_tik.ee.ethz.ch