Probabilistic Logic in CMOS (PCMOS)

1
Probabilistic Logic in CMOS (PCMOS)

• Krishna V. Palem?
• Kenneth and Audrey Kennedy Professor
• Rice University
• Director, Institute for Sustainable
  Nanoelectronics (ISNE) Nanyang Technological
  University(NTU), Singapore
• PCMOS Fabrication and Measurement Collaborators
• Pinar Korkmaz, Kiat-Seng Yeo , Zhi-Hui Kong

Intel Corporation, School of Electrical and
Electronic Engineering, Nanyang Technological
University This work was supported in part by
DARPA under seedling Contract F30602-02-2-0124
and an award from Intel Corporation to Georgia
Institute of Technology and by ISNE at NTU,
Singapore ? This author was supported in part by
the Moore distinguished faculty fellow program at
the California Institute of Technology (2008) and
by the VISEN center at Rice University The work
of this author was done as part of her PhD
research at the Georgia Institute of Technology.
2
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability
• Expressiveness and succinctness
• Probabilistic Boolean Logic(PBL)
• Probabilistic CMOS(PCMOS) Technology
• The value of probabilistic design
• Exploit property of PCMOS
• In conjunction with value of information
• Trade quality for cost
• Future directions

3
Impact

• A novel Probabilistic Boolean Logic(PBL)
• Validation of PBL through 0.18 µm CHRT(Chartered
  Semiconductor)
• technology fabrication.
• Using PBL to implement a ultra-low energy
  Hyper-Encryption system in CHRT
• 205 times more efficient through the
  energy-performance product metric over a
  conventional design
• Probabilistic arithmetic for ultra low energy
  signal processing
• A FIR used in H-264 realized with half the energy
  and negligible performance degradation
• Simulated using HSPICE and software models

4
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible

5
The Impediments to Moores Law

• Decreasing feature size
• Shrinking design margins
• Static variations
• Channel length, width
• Threshold voltage
• Interconnect (depth of focus)
• Dopant fluctuation

Gate Length Variations
Variations
Courtesy Dr Keith Bowman, Intel Corporation
6
Dynamic Variations as Impediments to Moores Law
Supply voltage variations
Thermal noise (amplified)
Temperature variations
Other dynamic variations
Courtesy Dr Keith Bowman, Intel Corporation
7
Abstraction in Design

• Abstractions have been used to design and
  automate the design of complex systems

Transistors
Truth tables
Logic circuits
Boolean Formulae
Input Output
0 1
1 0
Gates
Behavioral Abstraction
Structural Abstraction
Technology
8
An Ideal CMOS Inverter

• Corner case for an ideal deterministic inverter
• If Vin lt Vdd/2, Vout Vdd
• If Vin gt Vdd/2, Vout 0

• Corner case as a rule of thumb
• Is invariant as the output is observed over time
• Strictly depends on the input

Vdd
Digital 0
Digital 1
Vin
Vout
Vout
0
Vdd
An Ideal Inverter
9
Effect of Dynamic Variations on the Rule of
Thumb
Transistors
Truth tables
Logic circuits
Boolean Formulae
Input Output
0 1
1 0
Gates
Structural Abstraction
Technology
Behavioral Abstraction
If Vin lt Vdd/2, Vout Vdd If Vin gt Vdd/2, Vout
0
Rule of Thumb
In the presence of dynamic variations
Transistors
Truth tables
Noise
Logic circuits
Boolean Formulae
Input Output
0 1
1 0
Gates

?
?
?
?
What is the rule of thumb in this case ?
10
Effect of Dynamic Variations on the Rule of
Thumb(Contd.)

• What is the rule of thumb ?

Noise from the Dynamic variations
T2
T3
T1
Therefore, a single rule of thumb with two cases
does not capture essential information

Noise Voltage
Need to list many rules of thumb due to
uncertainty in the behavior of noise
At T1, If Vin 0.40 ltVdd/2, Vout Vdd
If Vin 0.40 gtVdd/2, Vout 0
Dropping many of these cases can lead to loss of
essential information
At T2, If Vin 0.52 ltVdd/2, Vout Vdd
If Vin 0.52 gtVdd/2, Vout 0
At T3, If Vin 0.60 ltVdd/2, Vout Vdd
If Vin 0.60 gtVdd/2, Vout 0
Inefficient/Incorrect design
11
How do we model this uncertain behavior?
Supply voltage variations.

• Specification of PBL independent of the
• particular physical perturbation
• Captured through the
• probabilistic parameter

Influenced only by the statistics of noise
Thermal noise
Temperature Variations
Model noise succinctly as a probabilistic
parameter
Rule of thumb that allows a probabilistic
parameter is a path to succinctness, which is a
central part of achieving efficiency for human
designers
Transistors
Truth tables
Noise
Probabilistic Boolean Logic circuits
ProbabilisticBoolean Formulae
Probabilistic Gates
Input Output
0 1
1 0

X
?
X
X
Structural Abstraction
11
12
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability
• Expressiveness and succinctness
• Probabilistic Boolean Logic(PBL)

Lakshmi N. B. Chakrapani and Krishna V. Palem, "A
Probabilistic Boolean Logic and its Meaning",
Rice University, Department of Computer Science
Technical Report, No. TR08-05, June
2008.Lakshmi N. B. Chakrapani, Probabilistic
Boolean Logic, Arithmetic and Architectures,PhD
Thesis, Georgia Institute of Technology, August
2008.
13
Probabilistic Boolean Logic

• Boolean Logic captures rules of thumb on input
  and output behaviors (functionality)
• Probability captures uncertainty
• Operators are correct with a probability p
• Operators are subscripted with p
• Incorrect with probability (1-p)
• Thermal noise, power supply noise and other
  dynamic perturbations
• Does not depend on the source of perturbation
• Only on statistics of the source which determines
  p

xx
xx
?
x
?
x ?
Input Input Outputx ?p y Outputx ?p y
x y 0 1
0 0 p 1-p
0 1 p 1-p
1 0 p 1-p
1 1 1-p p
?p (0p1)
14
The meaning of Probabilistic Boolean Logic

• Each probabilistic Boolean formula
• Is associated with a set of classical(deterministi
  c) Boolean formulae
• The probability that F behaves like one of these
  Boolean formula

Behaves like this 2 out of 3 times.
Formula F
01
2/3
And like this 1 out of 3 times.
Probabilistic Conjunction
Associated set of Boolean formulae
15
Considering More Complex Formulae

• For two probabilistic Boolean formulae F and G
• If the underlying family of deterministic Boolean
  formulae F and G and their probabilities are
  equivalent
• F is equivalent to G

Consider the circuit representation of a
probabilistic Boolean formula
Probabilistic De-Morgans Law
?
AND NOT P(OUT)
Correct Correct 2/3 3/4
Wrong Wrong 1/31/4
Correct Wrong 2/31/4
Wrong Correct 1/33/4
OR P(OUT)
Correct 7/12
Wrong 5/12
The obvious simplification
16
Properties of PBL
Probabilistic Distributivity
Identities Preserved

Theorem Probabilistic Boolean Logic is not
distributive
Probabilistic Associativity
( ( (x1Vp x2) Vp x3) Vp x4 )
( (x1Vp x2) Vp ( x3Vp x4 ) )

Theorem Probabilistic Boolean Logic is not
associative
17
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability
• Expressiveness and succinctness
• Probabilistic Boolean Logic(PBL)
• Probabilistic CMOS(PCMOS) Technology

S. Cheemalavagu, P. Korkmaz, K. Palem, Ultra
low-energy computing via probabilistic algorithms
and devices CMOS device primitives and the
energy-probability relationship, Proc. Int.
Conf. Solid State Devices and Materials (SSDM),
2004. P. Korkmaz, B. Akgul, K. Palem, L.
Chakrapani, Advocating noise as an agent for
ultra-low energy computing probabilistic
complementary metal-oxide-semiconductor devices
and their characteristics, Japanese J. of App.
Phys., April 2006.Pinar Korkmaz, "Probabilistic
CMOS (PCMOS) in the Nanoelectronics Regime", PhD
Thesis, Georgia Institute of Technology, December
2007
18
Effect of Dynamic Variations on the Rule of
thumb
Consider the design flow again.
Truth tables
Transistors
Noise
Input Output Output
Input 0 1
0 1-p p
1 p 1-p
ProbabilisticBoolean Formulae
Probabilistic Logic circuits
Probabilistic Gates

X
X
X
X
Structural Abstraction
Behavioral Abstraction
Technology
The previous section
This section
What do we have so far ?
19
CMOS Inverter as a Probabilistic Object

• Noise induced (energy) fluctuations
• Thermal noise
• Derive probability of error as a function of
  supply voltage
• and noise magnitude

Digital 1
Digital 0
Probability of 1 being treated as 0
Ideal case
Probabilistic case
Vin
Vout
Probability of 0 being treated as 1
Vout
0
Vdd
Sum of areas is equal to the probability of error
p(say)
By symmetry when Vin 0
Projected to be a significant concern in future
technology generations N. Sano, Increasing
importance of electronic thermal noise in
sub-0.1?m Si-MOSFETs, IEICE Transactions on
Electronics, vol. E83-C, pp. 12031211,
Aug.2000. L. B. Kish, End of Moores law
thermal (noise) death of integration in micro and
nano electronics, Phys. Letters A, Vol. 305,
2002.H. Li, J. Mundy, W. Paterson, D. Kazazis,
A. Zaslavsky, R.I Bahar, Thermally-induced soft
errors in nanoscale CMOS circuits, IEEE
International Symposium on Nanoscale
Architectures, 2007, pages 6269
20
Validation through fabrication of a CMOS inverter

• CMOS 0.18 ? m 1-Poly 6-Metal technology from
  Chartered Semiconductor (CHRT)
• Fabricated noise source different values of
  resistors (60k, 600k, and 2M ohm)
• Measurement methodology
• Agilent Technologies IC-CAP device modeling
  software
• HP 4142 source monitor unit

R Output swing Area (?m2)
60K 1.4 V 645
600K 1.7 V 6225
2M 1.8 V 12403
Probabilistic CMOS inverter output
For all three cases P 0.5 Power 665 uW at VDD
1.8 V and CL 20 pF
21
Varying probability of correctness
Can we control the probability of error ?
NSR and p relationship from fabricated data
Meas. Sim. AMI 0.5? 0.5? (yellow) TSMC 0.25?
0.25? IBM 65nm, 90nm
Vout
Reduce error probability by increasing Vdd
Vout
Law of Invariance NSR uniquely determines the
probability parameter p independent of the
Moores Law technology generation
22
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability in device abstraction
• Expressive and succinct
• Probabilistic Boolean Logic(PBL)
• Probabilistic CMOS(PCMOS) Technology
• The value of probabilistic design
• Exploit property of PCMOS

23
Efficient Designs Using Properties of PBL

• Encryption framework

• One bit message m to be transmitted from
  A(sender) to B(receiver)

• List L of length ?, of n-bit Boolean functions
• Such that Fi(0n) ? Fi(0n-11), where
  (only last bit is different)

• Choose the kth function Fk randomly
• Shared secret key k, 1 ? k ? ?, exists between
  both A B

Sender Receiver
most resource-intensive step of the algorithm

• Encoded bit c Fk(0n-1m) and transmit c, L (m
  is the last bit)

Sender

• Compute Fk(0n), Fk(0n-11) compare with c
• Retrieve m

Receiver
List of ? Boolean functions L
k
L
Only B knows which function A used to generate c
from m
B
Attacker can listen to traffic
Receiver
n-ary gate
m
0
c
c
0
A
Sender
0
Yan Zong Ding, Michael O. Rabin,
"Hyper-Encryption and Everlasting Security",
Lecture Notes In Computer Science Vol. 2285,
Proceedings of the 19th Annual Symposium on
Theoretical Aspects of Computer Science, 2002
24
Compressing the Size of the Circuit through the
Power of PBL

• Choose the kth function Fk randomly
• Shared secret key k, 1 ? k ? ?, exists between
  both A B

can be made less resource-intensive using PBL

• Encoded bit c Fk(0n-1m) and transmit c, L (m
  is the last bit)

a Boolean functions
A useful transformation A circuit with
probabilistic gates can be replaced with a
family of probabilistic inverters as inputs to a
deterministic circuit.
A single PBL formula can be a compact
representation of a family of Boolean functions
25
Compressing the Size of the Circuit through the
Power of PBL

• Choose the kth function Fk randomly
• Shared secret key k, 1 ? k ? ?, exists between
  both A B

can be made less resource-intensive using PBL

• Encoded bit c Fk(0n-1m) and transmit c, L (m
  is the last bit)

a inputs
A deterministic circuit with probabilistic
inverters as its inputs
A deterministic circuit with many random inputs
26
The Hyper-Encryption Circuit
Corresponds to a subset
Series of 2n-to-1 Multiplexers
Different sets of inverters
c
m
Encoding the m bit
Tree of XOR gates
Probabilistic Inverters
Secret Key k
Depending on the key choose an appropriate set
of inverters to the tree of XOR gates.
Basic blocks for the hyper-encryption algorithm
using Probabilistic inverters
27
Implementing Hyper-encryption
32 Probabilistic Inverters as Random Number
Generators
Probabilistic Inverter Noise Source Noise
Amplifier CMOS inverter
32 bits
64 5-bit Serial to parallel shift registers
(secret Key)
? ? ? ? ? ?
32-to-1 Multiplexer

Other 63 32-to-1 Multiplexers
5 bits
32 PCMOS Inverters
to XOR
???

Block B
64-bit XOR
m
to XOR
Block B
Output one encrypted bit per cycle
Technology Used CMOS 0.18 ?m, 1-Poly 6-Metal
technology from Chartered Semiconductor
28
Value of Probabilistic Design
A2
A1
PRNG based (Energy Performance )
Gain
10X
205X
PCMOS based (Energy Performance )
For producing one encrypted bit
B1
B2
Simulated using TSMC 250nm technology
Preliminary measurement results
Methodology
A1 A2 B1 B2
9.56 x10-8 Joules 3.13x10-6 sec 3.664 x 10-9 Joules 4x10-7 sec
PRNG HE Block Simulated 0

• Everything else measured

29
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability
• Expressiveness and succinctness
• Probabilistic Boolean Logic(PBL)
• Probabilistic CMOS(PCMOS) Technology
• The value of probabilistic design
• Exploit property of PCMOS
• In conjunction with value of information
• Trade quality for cost

30
Trading probability of correctness
Can we control the probability of error ?
Reduce error probability by increasing Vdd
Vout
Does it cost us ? If so, how much ?
Vout
31
The E-p relationship
Reduce error probability through higher Vdd
This relationship between Energy consumption and
the probability of correctness can be summarized
as follows
The First Law of PCMOS In any technology
generation (C) and constant noise magnitude (s)
the switching energy (E) grows with p. The order
of growth of E in p is asymptotically bounded
below by an exponential in p
Pinar Korkmaz, Bilge E. S. Akgul, Krishna V.
Palem and Lakshmi N. Chakrapani, Advocating Noise
as an Agent for Ultra Low-Energy Computing
Probabilistic CMOS Devices and Their
Characteristics Japanese Journal of Applied
Physics, SSDM Special Issue Part 1, April
2006. Stein, K.-U., Noise-induced error rate as
a limiting factor for energy per operation in
digital ICs, IEEE J. Solid-State Circuits, vol.
12, pp. 527530, Oct. 1977.
32
The Analytical E-p relationship

• Use the analytical model to develop a
  relationship between Energy and Probability of
  correctness

E(fJ) p
1 0.84
2.2 0.9
4.5 0.98
A Rule of thumb supporting a tradeoff
Energy-probability of correctness relationship
(E-p) for an inverter in 180nm CHRT technology
33
Validation of the First Law
p Energy Vdd
0.999 11 1.0
0.976 1.61 0.4
0.889 0.9 0.3

1. CMOS 0.18 ? m 1-Poly 6-Metal technology from
   Chartered Semiconductor (CHRT)
2. Supply voltage is varied from 0.3V to 1.8V
3. Inverter Load Capacitance 286fF

Energy-probability of correctness relationship
(E-p) for an inverter in CHRT 0.18?m technology
and Arizona State University PTM 32 nm technology
34
Modeling the Filtering Effect of the Noise by the
PCMOS Inverter
Basic Model
The new model
K1, K2, ? parameters fitted using
simulations Tn maximum frequency component of
noise

• When the sampling frequency (or the maximum
  frequency component)
• of the noise gt the maximum switching
  frequency of the inverter
• Noise is filtered by the inverter
• The analytically found p values are smaller than
  those that of the simulation results

Pinar Korkmaz, Bilge E. S. Akgul and Krishna V.
Palem ,Analysis of Probability and Energy of
Nanometre CMOS Circuits in Presence of Noise,
Electronics Letters, Vol. 43, Issue 17, Aug.
2007. 
35
Extending To Other Gates

• The Energy-probability relationship of a
  CMOS-based switch can be extended
• Consider XOR gate

Vdd P
0.4 0.854
0.8 0.975
1.2 0.998
Measured, Modeled Energy-probability of
correctness relationship for a XOR gate
36
Effect of Parameter Variations

• Effect of channel length variation
• 10 variation

Energy-probability of correctness relationship
(E-p) for an inverter for varying channel lengths
37
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability
• Expressiveness and succinctness
• Probabilistic Boolean Logic(PBL)
• Probabilistic CMOS(PCMOS) Technology
• The value of probabilistic design
• Exploit property of PCMOS
• In conjunction with value of information
• Trade quality for cost
• The value of probabilistic design

Best PaperCASES 2006

• Jason George, Bo Marr, Bilge E. S. Akgul and
  Krishna V. Palem, Probabilistic Arithmetic and
  Energy Efficient Embedded Signal Processing
  Proceedings of the Intl. Conference on Compilers,
  Architecture and Synthesis for Embedded Systems
  (CASES), Seoul, Korea, October 23-25, 2006
• Lakshmi N. B. Chakrapani, Kirthi Krishna,
  Lingamneni Avinash, Jason George and Krishna
  Palem, "Highly Energy and Performance Efficient
  Embedded Computing through Approximately Correct
  Arithmetic", International conference on
  Compilers, Architectures, and Synthesis for
  Embedded Systems, 2008.
• Lakshmi N. B. Chakrapani, and Krishna Palem,
  Probabilistic Arithmetic", Rice University,
  Department of Computer Science Technical Report,
  TR08-85, October 2008.

38
The value of probabilistic design
10
11
7
8

• Even a slight sacrifice of probability of
  correctness yields energy savings
• p ? 0.99 to p ? 0.85 for XOR gate
• 10.6x reduction in energy
• Use the First law to guide the tradeoff

39
H.264 Image Decoding using Probabilistic Design
Adders
Adder
FIR
Multipliers
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
MSB LSB
FIR
1
2
3
Vdd
Normal operation
2.5
BIVOS
Uniform voltage scaling
0.9
0
11 10 9 8 7 6 5 4 3 2 1 0 Bit Position
Bit Error Rate
BIVOS
Uniform Voltage Scaling
0.18
Normal operation
0
11 10 9 8 7 6 5 4 3 2 1 0 Bit Position

• Probabilistic Biased Voltage Scaling or BiVoS

40
Outline

• Device variations and perturbations
• Current-day (deterministic) logics are no longer
  adequate
• Designing computing systems using current day
  design methodologies based on traditional logics
  are no longer possible
• The role of probability
• Expressiveness and succinctness
• Probabilistic Boolean Logic(PBL)
• Probabilistic CMOS(PCMOS) Technology
• The value of probabilistic design
• Exploit property of PCMOS
• In conjunction with value of information
• Trade quality for cost
• The value of probabilistic design
• Future Directions

41
Probabilistic Design for Ultra-low energy devices

• Mobile Embedded Devices

• Education

• Medical Prosthetics

A low power solar powered visual device for
educating in rural areas with limited access to
electricity
Auditory and Visual Prosthetic Design
Cell Phone Lite

• Collaborators
• Yeo Kiat Seng, NTU
• Vincent Mooney, NTU

High-Fidelity Video and Graphics
Collaborators 1. Al Barr, Caltech

• Collaborators
• Al Barr, Caltech
• Danny Petrasek,Caltech

• Collaborators
• Jayanthi Sivaswamy
• NGO - VIDAL

Perception based design with a neuro-biological b
asis.
Perceptual limitations
42
Putting It All Together - An Architectural Vision

• Substantial within-die variation is expected in
  future architectures
• Threshold Vth voltage variation is an example
• Variation is known only post manufacturing
• Could result in upto 30 variation in speed1
• Ameliorate the effects of variations
• Design independent techniques (e.g Vth
  variations)
• Test blocks for speed and leakage
• Use bidirectional adaptive body-biasing circuits
  to compensate2
• Design specific techniques (e.g ripple carry
  adder)
• Use faster blocks for most significant bits
• What is an architecture amenable to such
  techniques ?

Configurable Interconnect
Storage for variation information
Block 1
Block 2
Block 3
Slowest
Fastest
Slow
Least Significant
MostSignificant
Store information about variation Use
information for design independent techniques
like adaptive body biasing
Use information for design dependent techniques
like mapping design on to reconfigurable fabric
Logic blocks which comprise a FIR filter
Blocks are tested to determine their behaviors
Reconfigured chain of blocks to implement FIR

• Collaborators
• Jim Meindl, Georgia Tech
• Raghu Murali, Georgia Tech

1S. Borkar, T. Karnik, S. Narendra, J. Tschanz,
A. Kesha varzi, and V. De. Parameter variations
and impact on circuits and microarchitecture. In
ACM/IEEE 40th Design Automation Conference
(DAC-03), pages 338342, Anaheim, CA, June 2-6
2003. 2Tschanz, J.W. Kao, J.T. Narendra, S.G.
Nair, R. Antoniadis, D.A. Chandrakasan, A.P.
De, V. Adaptive body bias for reducing impacts
of die-to-die and within-die parameter variations
on microprocessor frequency and leakage, In IEEE
Journal of Solid State Circuits, pages 13961402,
November 2002.