LinkonChip LoC Design for LAr Frontend Readout

1
Link-on-Chip (LoC) Design for LAr Front-end
Readout

• Ping Gui, Peiqing Zhu, Wickham Chen, Junheng
  Zhang
• Electrical Engineering Department
• Andy Liu, Annie Xiang, Jingbo Ye, Ryszard
  Stroynowski
• Physics Department
• DoE Meeting
• Physics Department
• Southern Methodist University
• Dec. 14, 2006

2
Outline

• Link-on-Chip Architecture
• Silicon-on-Sapphire (SoS) Test Chip
• Measurement results
• Link-on-Chip Design
• Ring-VCO-based PLL Serializer
• LC-tank PLL
• VCSEL Driver Circuit

3
Link-on-Chip Architecture
Flip-chip bonding
PLL and clock generator
REFclock
Laser
encoder
Laser Driver
serializer
Parallel Data
TX
transmitter Module
Optical data
Receiver Module
Parallel Data
Flip-chip bonding
Photonic
De- serializer
Decoder
PIN
TIA/LA
Clock/Data recovery
REFclock

• Improve performance
• No off-chip high speed lines
• Flip-chip bonding reduces capacitance and
  inductance
• Reduce power consumption
• No 50-Ohm transmission lines between chips
• Designed and Implemented in Silicon-on-Sapphire
  technology

4
Silicon-On-Sapphire Test Chip
5
Radiation Effects on PMOS and NMOS
Measured NMOS Ids v.s. Vgs curve
Measured PMOS Ids v.s. Vgs curve
Post rad(4Mrad)
Post rad (4Mrad)
After annealing
After annealing
Before rad
Before rad
Vt shifted by 0.2V Off-current 90nA after
annealing
Vt shifted by 0.17V Off-current 800nA after
annealing
6
2.6-Ghz Voltage-Controlled Oscillator (VCO)
measurement
Histogram of Clock Period
VCO output jitter measurement
2.8ps/div
Measured VCO output at 2.6Ghz
7
PLL Components Measurement
div-by-16 output Input _at_ 2.5GHz Output_at_ 156MHz
PFD output measurement _at_156Mhz 1ns phase
difference Between refclk and divclk
8
Phase-Locked Loops (PLL)

• Self-biasing Ring type VCO
• Remove process technology and environmental
  variability, low input tracking jitter, Wide
  operating frequency range
• VCO with differential buffer delay stages
• Phase-frequency detector
• equal short duration output pulses for in-phase
  clock inputs
• Charge-pump with symmetric load

1 J. G. Maneatis, low-Jitter
Process-Independent DLL and PLL Based on
Self-Biased Techniques, IEEE JSCC, Vol. 31, No.
11, Nov. 1996.
9
PLL and Clock Generator
10
1.25-GHz Self-Biasing PLL
Vcntrl1
Vcntrl2
Charge
Charge
PFD
S2D
vdd
gnd
Pump1
Pump2
d
i
v
start
5
up
VCO
div4
D2S
Bias Gen
11
2.5-Gbps Serializer Architecture
(1,5,9,13,17)
SR1
Bits 1,3,5,7,9, 11,13,15,17,19
5 bit
20-bit Word Latch
Mux1
(3,7,11,15,19)
SR2
5 bit
Serial output
Latch
20bit
Mux3
SR3
5 bit
(2,6,10,14,18)
Mux2
Latch
Ref_clk
(4,8,12,16,20)
SR4
5 bit
Latch
Bits 2,4,6,8,10, 12,14,16,18,20
Shift registers
Half bit clk (625MHz)
Word clock (125MHz)
Load clk (125MHz)
Bit clk (1.25GHz)
PLL Clk generator
12
2.5Gbps Serializer Layout
13
2.5Gbps Serializer PLL Clock Generator
Serializer
Clk generator
PLL
14
Serializer Simulation at 2.5-Gbps
15
Serializer Simulation at 3.2Gpbs
16
LC-based PLL

• Inductors and Capacitors are inherently radiation
  hard
• Lower phase noise
• Allowing for higher data rate optical links
• Offering comparative study of the
  radiation-tolerance between Ring VCO-based PLL
  and LC-based PLL
• Tuning range may be narrower

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Wide-band LC-Oscillator
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VCO Simulation
Pre-rad simulation
Post-rad simulation
VCO Tuning Range 2.3Ghz-5 Ghz
2.3Ghz-4.8 Ghz
Phase noise -130dBc/Hz _at_ 1 MHz offset
-128dBc/Hz _at_ 1 MHz offset
19
6-GHz Current-Mode-Logic Divider
div-by-16 Output
div-by-16 Output
Input _at_6GHz
Input _at_6GHz
Pre-rad simulation
Post-rad simulation
20
Complete LC PLL Design
21
LC-Oscillator Layout
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Complete LC PLL Simulation Results
PFD output when inputs out of phase
PFD output when inputs in phase
VCO output _at_3.6GHz
PLL locks within 400ns
23
5-Gbps VCSEL Driver Circuit
24
Conclusion

• SoS Test chip measurements are completed.
• Serializer, Ring PLL, LC PLL design are completed
• VCSEL driver and line driver are being designed
  and integrated
• Prototype chip tape-out on Feb. 1st, 2007