CSE 7381

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Lecture 4 Case Study MIPS 4000Instruction Set
Limitations, Exceptions

• Prof. Fatih Koçan
• CSE 7/5381 Computer Architecture
• Fall 2002
• Adapted from Pattersons Slides

CSE 7381 Computer Architecture
FK.F02 1
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Review Summary of Pipelining Basics

• Hazards limit performance
• Structural need more HW resources
• Data need forwarding, compiler scheduling
• Control early evaluation PC, delayed branch,
  prediction
• Increasing length of pipe increases impact of
  hazards pipelining helps instruction bandwidth,
  not latency
• Interrupts, Instruction Set, FP makes pipelining
  harder
• Compilers reduce cost of data and control hazards
• Load delay slots
• Branch delay slots
• Branch prediction
• Today Longer pipelines (R4000) gt Better branch
  prediction, more instruction parallelism?

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Case Study MIPS R4000 (200 MHz)

• 8 Stage Pipeline
• IFfirst half of fetching of instruction PC
  selection happens here as well as initiation of
  instruction cache access.
• ISsecond half of access to instruction cache.
• RFinstruction decode and register fetch, hazard
  checking and also instruction cache hit
  detection.
• EXexecution, which includes effective address
  calculation, ALU operation, and branch target
  computation and condition evaluation.
• DFdata fetch, first half of access to data
  cache.
• DSsecond half of access to data cache.
• TCtag check, determine whether the data cache
  access hit.
• WBwrite back for loads and register-register
  operations.
• 8 Stages What is impact on Load delay? Branch
  delay? Why?

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Case Study MIPS R4000
IF
IS IF
RF IS IF
EX RF IS IF
DF EX RF IS IF
DS DF EX RF IS IF
TC DS DF EX RF IS IF
WB TC DS DF EX RF IS IF
TWO Cycle Load Latency
IF
IS IF
RF IS IF
EX RF IS IF
DF EX RF IS IF
DS DF EX RF IS IF
TC DS DF EX RF IS IF
WB TC DS DF EX RF IS IF
THREE Cycle Branch Latency
(conditions evaluated during EX phase)
Delay slot plus two stalls Branch likely cancels
delay slot if not taken
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MIPS R4000 Floating Point

• FP Adder, FP Multiplier, FP Divider
• Last step of FP Multiplier/Divider uses FP Adder
  HW
• 8 kinds of stages in FP units
• Stage Functional unit Description
• A FP adder Mantissa ADD stage
• D FP divider Divide pipeline stage
• E FP multiplier Exception test stage
• M FP multiplier First stage of multiplier
• N FP multiplier Second stage of multiplier
• R FP adder Rounding stage
• S FP adder Operand shift stage
• U Unpack FP numbers

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MIPS FP Pipe Stages

• FP Instr 1 2 3 4 5 6 7 8
• Add, Subtract U SA AR RS
• Multiply U EM M M M N NA R
• Divide U A R D28 DA DR, DR, DA, DR, A, R
• Square root U E (AR)108 A R
• Negate U S
• Absolute value U S
• FP compare U A R
• Stages
• M First stage of multiplier
• N Second stage of multiplier
• R Rounding stage
• S Operand shift stage
• U Unpack FP numbers

A Mantissa ADD stage D Divide pipeline
stage E Exception test stage
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R4000 Performance

• Not ideal CPI of 1
• Load stalls (1 or 2 clock cycles)
• Branch stalls (2 cycles unfilled slots)
• FP result stalls RAW data hazard (latency)
• FP structural stalls Not enough FP hardware
  (parallelism)

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Instruction Level Parallelism (ILP)

• ILP Overlap execution of instructions
• Related instructions ? partial/limited overlap
• Approaches to exploiting ILP
• Largely dynamic and depend on the HW to locate
  the parallelism (desktop/server markets)
• Pentium III 4, The Athlon, MIPS R10000/12000,
  Sun UltraSPARC III, Alpha 21264
• Static and rely on SW (the embedded market)
• New IA-64 architecture and Intels Itanium

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What limits ILP?

• Some features of programs? Yes!
• Some features of processors? Yes!
• Mapping between program structure and hardware
  structure
• A program property will ACTUALLY limit
  performance and under what circumstances

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Pipeline CPI Formula

• Pipeline CPI Ideal Pipeline CPI Structural
  Stalls Data Hazard Stalls Controls Stalls
• Ideal Pipeline CPI a measure of the maximum
  performance attainable by the implementation.
• Reduce stall cycles ? Minimize the overall
  pipeline CPI ? Increase the instructions per
  clock (IPC)

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Pipeline Stall

• The Control Unit (CU)
• insert the pipeline stall
• freeze the instructions that are in the IF and ID
  stages
• IF ID EX MEM WB
• I5 I4 I3 I2 I1

Where is the control information ? In the
pipeline registers !
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How to stall the pipeline?

• Change the control portion of the ID/EX pipeline
  register to all 0s
• a NOOP instruction. DADD R0,R0,R0
• Recirculate the contents of the IF/ID registers
  to hold the stalled instruction

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Forwarding/Bypassing/Short-circuiting

• Observation Pipeline registers contain both
• the data to be forwarded
• the source and destination registers fields

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Stopping Restarting Execution

• Restarting save the PC of the instruction at
  which to restart
• Restarted instruction
• NOT a BRANCH
• Continue with the next instruction
• a BRANCH
• Reevaluate branch condition

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3 Steps for Pipeline State Saving

• Force a trap instruction into the pipeline on the
  next IF
• TRAP transfer to OS at a vectored address
• ERET Return to user code from an exception
  restore user mode
• Until the trap is taken,
• turn off all writes for the faulting instruction
• And for all instructions that follow in the
  pipeline
• Place 0s into the pipeline latches of all
  affected instructions in the pipeline
• The exception-handling routine in the OS receives
  the control, save the PC of the faulting
  instruction

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Delayed Branches

• The instructions in the delayed branch slots may
  not be sequentially related
• Save restore as many PCs as the length of the
  branch delay 1
• Done in the 3rd step
• RFE in MIPS to return from the exception routine

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Precise Exceptions

• If the pipeline can be stopped so that the
  instructions just before the faulting instruction
  are completed and those after it can be restarted
  from scratch
• ? The pipeline has precise exceptions
• Page fault exception at MEM stage, which
  instruction to restart ? Which one(s) to complete?

IF ID EX MEM WB
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Faulting Instructions

• Handling some exceptions requires that the
  faulting instruction have no effects.
• Other exceptions e.g. FP exceptions
• The faulting instruction writes its result before
  the exception can be handled
• HW is required to retrieve the source operands,
  even if the source is also destination!
• FP operations require long cycles, other
  instructions may have updated the source operands
• Two modes of operation supported by some CPUs
  Precise and Other

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Support for Precise Exceptions

• At a minimum, any processor with demand paging or
  IEEE arithmetic trap handlers
• ? must be precise (in the HW or with SW support)
• For Integer Pipelines
• Easy to create precise exceptions
• Support for precise exceptions for memory
  references
• ? Always provide precise exceptions for the
  integer pipeline

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Implementing Precise Exceptions for the MIPS
Integer Pipeline
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Implementing Precise Exceptions for the MIPS
Integer Pipeline

• Multiple exceptions may occur in the same cycle
• LD ? page fault
• DADD ? arithmetic exception
• First, handle page fault, and restart
• The second exception will reoccur

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Out-of-order Occurrences of Exceptions

• Precise exceptions requires us to first handle LD
  exception and then DADD exception.
• Exception is recorded in a status vector
  associated with that instruction
• Control signals are turned off (register or
  memory writes)
• The status vector is carried along with the
  instruction
• At the WB stage, the status vector is checked

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Instruction Set Complications

• MIPS
• Commit stage
• The end of the MEM stage or the beginning of the
  WB stage
• Some processors, IA-32 architecture
• Autoincrement addressing mode
• State is updated in the middle of the instruction
  execution

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Instruction Set Complications

• Avoid the state update before the instruction
  commit
• Difficult/Costly approach if there is dependence
  on the updated state
• E.g. a VAX instruction that autoincrements the
  same register multiple times
• Updating memory during execution, e.g. the string
  copy operations
• The state of the partially completed instruction
  is always in the registers, e.g. IA-32
• Saved on an exception and restored later

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Instruction Set Complications

• Odd bits of state ? additional pipeline hazards
  or extra HW to store and restore
• condition code
• Implicitly set condition codes
• Decouple the evaluation of the condition from the
  actual branch
• Difficulties in scheduling any pipeline delays
  between setting the condition code and the branch
• Processor decides when the branch condition is
  fixed
• When the condition code has been set for the last
  time before the branch
• Delay the branch condition evaluation until all
  previous instructions have had a chance to set
  condition code
• Treat condition code as operand? RAW hazard

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Instruction Set Complications

• Multicycle operations
• 1?100s cycles
• 0?100s memory acccesses
• Data hazards are very complex and occur both
  between and within instructions
• ? Pipelining at the Instruction Level is
  diffucult
• ? Pipeline the microinstruction execution
• VAX 8800 IA-32