Rao R Tummala

1
Design-Build-Operate An Undergraduate
Microelectronics Packaging Education Reform at
GeorgiaTech
Rao R Tummala Director
NSF-ERC Conference Washington, DC
November 7, 1999
2
Next-Generation System Needs and Functions
Auto
Digital Wireless Communication
700
TZ-802B
600
)
500
cm³
TZ-803B
400
Dyna
-TAC
Volume (
300
200
Micro-TAC
100
TZ-804B
Source JTEC
0
80
85
90
95
Analog, RF
MEMS
Consumer
Computer
10M
ECL
1M
Cost/Performance (/MIPS)
100K
Mainframes
10K
CMOS
1K
1X
PCs
100
10
1
1970
1980
1990
2000
High Bandwidth
Year
High-speed Digital
3
SOP Microelectronics for the 21st Century
YESTERDAY
TODAY
MCM
MCM
Integrated Digital Packaging SOB / MCM/DCA
Discrete Packaging System-on-Package-on-Board
(SOPOB)
Wafer-level Test Burn-in I/O
SLIM Package SOP
SLIM
4
Industrys First MCM
5
Giga-scale IC Integration Issues
Fundamental Issues IC Signal Speed Latency SiO2
Dielectric Insulation
Technology
MOSFET Intrinsic
Response
Generation
Switching Delay
Time
(L
1mm)
int
1.0 um
10
ps
1
ps
.05 um
1
ps
100
ps
6
Research Vision Goals
Time
Discrete Today
SOP Tomorrow

• GOALS
• 10x Each
• Performance
• Cost
• Reliability
• Size

7
SOP Research Strategy
Reliability
Thermal Management
Large Area Intelligent Manufacturing
RF Design
SOP
Assembly
Electrical Test
Integral Passives
System Design
Digital Package Design
High Density Wiring
8
System-On-Package, SOP
Wafer Level Packaging
Thermal Management
High Bandwidth Optical
Flip-Chip Assembly
Integrated O
RF and Analog
Dielectric
High Speed Digital
Microvia
RF
Conductor
9
Fundamental Research Projects at PRC

50. Thermo-mechanical Modeling 51. Large Base
Substrate 52. Flexible Flip-Chip 53. Dry Film
Studies 54. Micro-Spring Analysis 55. Finite
Element Analysis 56. Flip-Chip Analysis 57.
Thermo-mechanical Analysis 58. Adhesion -
Lehigh 59. SLIM Reliability - NUS,
Singapore
60. Spray Cooling 61. Vibrational Spray
Cooler 62. Microjet Enclosures 63. Heat Pipe 64.
SLIM Microjet Cooling 65. Sealed Liquid/Two
Phase Cooling - Minnesota
43. Acoustic Sensor 44. Via Formation 45. RIE
Control 46. Integral Capacitor 47.
Optimization 48. Meniscus Coating 49. RIE
Diagnostics
ROADMAP
ROADMAP
66. Low Cost Packaging 67. Vertical
Interconnects 68. MM Wavelength
multilayer 69. Embedded RF 70. RF Pkg. -
Illinois
Fundamental Level
Thrust Level
Reliability
Large Area Mfg.
Thermal
29. Next-generation Flip-Chip 30. Ultra-fine
Pitch Printing 31. Wafer Scale Packaging 32.
Underfill Materials 33. Fast Flow Underfills 34.
GaAs Flip-Chip 35. Conductive Adhesives 36.
Environmental Conscious Materials 37. Reworkable
Underfills 38. System-on-chip 39. Metal Adhesion
to Substrates 40. Chip-on-Board Encapsulant 41.
Fundamental Limits of DCA - Fraunhofer,
Germany 42. Green Packaging - Sweden
71. Alignment Tolerance 72.
Low cost OE 73. Optical interconnects 74.
Thin Film Integration for RF 75. Polymer
Waveguides 76. Opto Interface Circuits
System Level
RF
SOP
Large Cool Chip Prototype
OE/RF Video Link Prototype
Opto
77. Substrate Test 78. High Speed Functional
Test 79. Parallel Functional Test 80. Mixed
Signal Test 81. New Test Methods - Michigan St
Assembly
Test
Chip-to-Chip Comm. Prototype
SOP
82. SOP Library of RLCs 83. Placement
Routing Algorithms 84. Global
Interconnect
Integral Passives
Design
16. MOCVD 17. Integral Inductors 18.
High-k Polymers 19. Large Area Capacitors 20.
High-k Composites 21. Nanocomposite
Capacitors 22. Integral Resistors 23. Cost
Modeling of Passives 24. Passives Modeling 25.
Predictive Modeling 26. Embedded Resistors
27. Resistor - KAIST Korea 28.
Nanomaterials- IISc,
India
High Density Wiring
Process
SLIM
Baseline
85. Predictive Modeling 86. Mixed Signal Design
Tools 87. SSN Analysis 88. TDR Characterization 89
. Mixed Signal Design - Oregon State
1. Fine-line Technology 2. Non-formaldehyde
electroless copper 3. P-4 Vialess Process 4. Dry
Film Dielectrics 5. Porous Dielectrics 6.
SLIM Base Substrate 7. E-beam Curing
8. Microwave Curing 9. Dielectric
Characterization 10. Photo-polymer
Dielectrics 11. Dielectric Modeling 14.
Ultrafine Laser 12. Avatrel Dielectric 15.
Low-k Airgaps 13. Palletization approach for
base substrate
ROADMAP
ROADMAP
10
PRC Vision 89,000-Person Journey in New SOP
Technology
ROLE IN INDUSTRY
LEVEL
EDUCATIONAL CHARACTERISTICS
Junior College

• Manufacturing
• Prototyping

• Hands-on tool processes

B.S.

• Product Development
• Manufacturing

• System-level classroom theory
• Complete hands-on product development cycle
  education
• Industry perspective

M.S.

• Product Development

• Appetite for individual and team research, good
  communication skills
• Business, management, global markets culture

Ph.D.

• R D

• Deep understanding at system fundamental level
• Capable of RD in any area of microelectronic
  systems packaging
• Team Research

Currently Employed 58,000 Projected Need (2008)
89,000
11
Research Appetite and Team Research
Fundamental Theory classes
PRC Undergraduate Education Reform
Systems Level
Design Tools
Complete Product Development Cycle
Text Book
Industry Perspective