Combinational Hardware False Path Identification without Search

1
Combinational Hardware False Path Identification
without Search

• Graduate Student Thesis
  Director
• Gagandeep S. Sandha Prof. Michael L.
  Bushnell

December 20, 2006 Dept. of Electrical Computer
Engg., Rutgers Univ.
2
Outline

• Introduction
• Motivation
• Problem Statement
• Prior Work
• Our Work
• Results and Discussion
• Future Work
• Conclusion

3
Introduction

• Fault-Independent solution to the False Path
  Identification problem in circuits
• Computation without search
• Efficiency in CPU time and memory usage
• Applies to Combinational Circuits
• Finds more false paths in benchmark circuits than
  any prior method
• Identifies specific false paths

4
Motivation

• Critical path delay 5 sec. (Path A,D,C)
• True longest path delay 2 sec. (Path B,B1,C)

False Path A path that is functionally false.
For delay-fault testing, a transition passing
through this path can never be realized at the
output.
5
Problem Statement

• Propose a fault-independent false path
  identification method for combinational circuits
  without search
• Introduce dominator theory for reducing
  computational complexity
• Quickly determine a large number of false paths
  in any circuit

6
Prior Work

• False Path Identification Methods
• Implication Graph Basics

7
Prior Work False Path Identification Methods

• Automatic Test Pattern Generation (ATPG) based
  (Zeng et al., Bhadra et al.)
• Satisfiability (SAT) based (Ringe et al., Marques
  et al.)
• Binary Decision Diagram (BDD) based (McGeer
  Brayton, Kontouris et al.)
• Fault Simulation based (Gharaybeh et al.,
  Chakraborty et al.)

8
Prior Work Implication Graph Basics

• Graph represents Boolean expressions
• Nodes represent literals, edges represent
  implications

1
2
1
2
3
9
Implication Graph Basics
Direct Implication Partial Implication
If 1 and 2 are 1 then 3 is 1
1
2
1
2
3
10
Implication Graph Basics
Backward ANDing nodes used to represent backward
implications
The complete IG for a two-input AND gate
1
2
1
3
2
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Implication Graph Basics

• IG for a circuit

3
4
1
2
4
5
4
3
1
2
IG Implication Graph
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Implication Graph Basics

• IG for a circuit

1
3
2
1
5
2
3
IG Implication Graph
13
Computing Transitive Closure

• Transitive closure of a directed graph contains
  the same set of nodes as the original graph

2
4
3
14
Our Work

• Dominator Theory
• Theory of False Paths
• Theorems for False Path Identification (FPI)
• Top Level Algorithm for FPI
• Example for FPI

15
Dominator Theory for Implication Graphs
A
L
B
I
N
R
C
K
J
D
M
E
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Dominator Theory for Implication Graphs
A
L
B
I
N
R
C
K
J
D
M
E
Basis Point Point of complete reconvergence and
can be assigned values independently like
HEADLINES
Basis Point
Mercer et al., A Topological Search Algorithm
for ATPG, IEEE DAC 1987 Fujiwara , On the
Acceleration of Test Generation Algorithms, IEEE
Trans. Comp., 83
17
Dominator Theory for Implication Graphs (contd.)
A
L
B
I
R
N
K
C
J
D
A
M
E
Output
CIRCUIT
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Dominator Theory for Implication Graphs (contd.)
A
L
B
I
R
N
C
K
J
D
A
M
E
Output
Absolute Basis Dominator
CIRCUIT
19
Theory of False Paths

• Path delay fault classification
• Singly testable (ST) Iff ? vector pair ltv1, v2gt
  s.t. a transition can be initiated at path input,
  all side-inputs take non-controlling values.
• Multiply testable (MT) Iff ? a set of
  singly-untestable paths incl. the MT path s.t.
  transitions can be initiated at P.I.s of
  associated faults and all of side-inputs assume
  non-controlling values.
• ST-Dependent Related to one or more other ST
  paths. Can propagate transition iff the related
  ST paths can.

For path delay fault classification (ST, MT,
ST-Untestable paths) Gharaybeh et al.,
Classification and Test Generation for Path-Delay
Faults Using Single Struck-at Fault Tests, JETTA
1997
20
Theorems for FPI Theorem 1

• If ltv1,v2gt is an input vector sequence applied to
  a singly testable (ST) path P having a delay
  fault, then
• If application of ltv1gt at path input in time
  frame (TF) 1 introduces an implication edge (a
  Oa) Node a is unobservable at output path
  P is false.

Applies to all the 8 conditions of Agrawal et
al., ATS 96.
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Theorems for FPI Theorem 1 (contd.)
Corollary 1 This condition is true if (a
Oa) holds true in either TF1 (application of
ltv1gt) or TF2 (application of ltv2gt).
Corollary 2 This condition is true not only for
the input node a, but any internal node along
the path P.
Applies to all the 8 conditions as in Agrawal
et al., ATS 96.
22
Theorems for FPI Theorem 2

• Let ltv1,v2gt be an input vector sequence applied
  to a set of singly untestable PDFs, including a
  multiply testable (MT) fault.
• Also, let D be the dominator of various singly
  untestable paths including the MT fault.
• If application of ltv1gt causes (D OD), then D
  is unobservable at circuit output and the
  corresponding MT fault is false.

Corollary This holds if above condition is true
in either TF1 (application of ltv1gt) or TF2
(application of ltv2gt).
Applies to all the 8 conditions of Agrawal et
al., ATS 96.
23
Theorems for FPI Theorem 3

• If an Absolute Basis Dominator (ABD), B, exists
  in a circuit, then if the input vector sequence
  ltv1,v2gt causes the implication (B OB) to be
  true, then the ABD is redundant and any path P
  passing through B is false.

Corollary 1 All nodes in the fault cone of B are
redundant. Corollary 2 Any path through the
nodes in fault cone of B is false.
Applies to all the 8 conditions of Agrawal et
al., ATS 96.
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Algorithm

• Parse circuit and build IG for each gate
• Preprocessor stage I Perform static timing
  analysis (STA)
• Preprocessor stage II Dominator Theory
  Application
• Compute Transitive Closure (TC)
• for (var 0 var lt N var)
• Initiate a rising/falling transition in var path
• Update transitive closure using TC routine
• If an ABD satisfies theorems for FPI, path is
  false
• Else
• Apply FPI condition at other nodes in the path

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Example
d
b
Falling Transition through Path a,d,c
d
b
O
O
d
b
Partial Implication Graph for Time Frame 1
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Example (cont.)
d
b
Falling Transition through Path a,d,c
d
b
1
O
O
O
c
d
b
Partial Implication Graph for Time Frame 2
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Results
50
50
49
49
49
43
23
2
1
0
28
Results (cont.)
100
98
99
100
98
66
51
2
1
0
29
Results (cont.)
150
148
149
150
148
91
71
2
1
0
30
Memory Usage
31
CPU Time
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Validation of Our Work

• Using VNRSEST A program to find untestable
  (false) timing paths in circuits
• Input the specific false paths detected as false
  by our work to this program
• This approach would establish the correctness of
  our method to detect false paths

Srinivas et, al., Flags and Algebra for
Sequential Circuit VNR Path Delay Fault Test
Generation, Proc. of Intl. Conf. on VLSI Design,
Jan. 1997
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Comparison of Our Work
Y False Paths Present N No False Paths Present
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Limitations

• Incompleteness
• Incompleteness in algorithm
• Incompleteness in FPI theorems
• Incomplete graph condensation
• Theory for application to sequential circuits

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Conclusion

• First fault independent false path identification
  method
• Efficient in computational complexity
• Moderate memory usage
• O(N) algorithm in terms of number of gates in a
  circuit
• An incomplete approach, yet quickly finds a large
  number of false paths in any circuit

36
Future Work

• Sequential circuit false path identification
• Complete set of false path detection theorems
• Dominator theory extension

37
Thank You

• Questions?