CPLD

1
PLD bypass (Clk, Trig, Abort only)
3
CPLD
VME Backplane
Front-panel
NIM In
Enables and Mapping
10
B-Sigs Out
4
Push-Buttons
3
Trigger Delay
GeogAddr
5
VME Interface
Registers
NIM Out
Address Bus
32
10
Repetitive Trigger Generate
Data Bus
16
L-Sigs Out
10
40
VME Control
30
V-Sigs Generate
4x Hex Switch
BaseAddr
16
Delay Unit 1
Delay1Set
6
Trigger Abort Logic
12.5MHz IntClk Generate
Delay Unit 2
50 MHz Clock
Delay2Set
LocalClk
6
Trigger Board Block Diagram