School of Electrical Engineering

1
RESEARCH WORK

• Janusz Starzyk
• School of Electrical Engineering
• and Computer Science

2
Research Topics

• Virtex - FPGA Design of GPS Receiver
• Modeling and Test of Mixed Systems with Embedded
  Software
• CAD Tools for Circuit Analysis and Test
• Neural Network Data Classification
• Focused Reducts and Rough Sets in ATR
• Design of Self-Organizing Neural Network
  Architectures (Analog and Digital)
• Design of Dynamically Reconfigurable Architecture
  for Mobile Communication Applications

3
Graduate Students

• PhD students
• Al_Aqeeli, Abdulqadir
• Alsolaim, Ahamd
• Ding, Mingwei
• Guo, Yongtao
• Liang, Jing
• Liu, Dong
• Nelson, Dale
• Pang, Jing
• Zeng, Yujing
• Zou, Jun

• MS Students
• Chang, Ivan
• Lin, Tao
• Liu, Tsun-Ho
• Norris, Eugene
• Gunavardena, Sanjeev
• Zhou, Zen

4
Research Sponsors

• Federal Aviation Administration
• National Institute of Standards and Technology
• Air Force Office of Scientific Research
• Wright Laboratories
• Sarnoff Research Corporation

5
FPGA Design of GPS Systems
Abdulqadir Alaqeeli, Yongtao Guo, Jing Pang

• GPS Space Segment

24 satellites 6 Orbital planes 55
degrees inclination 20 200 km above the
Earth's surface 11 hours 58 minute orbital
period Visible for approximately 5 hours
above the horizon
6
GPS Positioning Signals
7
GPS Receiver
Front End Structure
8
GPS Receiver
Signal Acquisition / Signal Tracking
9
Satellite Signal Anomalies

• Focus on Signal Quality Parameters
• Carrier-to-Noise Ratio
• Shape of Correlation Function
• False Acquisition Peaks
• Code-Carrier Divergence
• Sudden Change in Code and/or Carrier
• Change in the Satellite Code

10
GPS Block Processing

• The following parameters are estimated using1-ms
  blocks of sampled data
• Code Phase
• Frequency and Carrier Phase
• Carrier-to-Noise Ratio
• No tracking loops are used !

1 ms 5000 samples
11
GPS Block Processing

• Sampled Satellite Signal Model

i, represents ith ms
12
Code and Carrier Frequency Acquisition
13
GPS Receiver
Software Simulation With MATLAB
Result
14
GPS Receiver signal acquisition
Hardware Implemented on Virtex FPGA
15
GPS Receiver
Hardware Implementation
FRE_SEARCH for j in 1 to 10 loop
ij SIN_COS_MODULOR(sv_data,i,1,svi)
SIN_COS_MODULOR(sv_data,i,2,svq)
TO_COMPLEX(count,svi,svq,svi_svq)
FFT_IFFT_TRANSFER(count,svi_svq,sv_f,tru
e) COMPLEX_MULTIPLY(sv_f,caf,sv_f_caf
) FFT_IFFT_TRANSFER(count_fft,sv_f_ca
f,sv_c,false) --vector multiplying
POWER_DETECTOR(sv_c,Y_E(i)) if
Y_E(i)gtMAX_POWER then MAX_POWER
Y_E(i) MAX_FREQ integer(fr)integer(freq_s
ta)(i-1)integer(freq_step) end
if end loop
Result Just as MATLAB simulation result
16
GPS C/A Code Generator
Jing Pang

• PRN(pseudo-random noise) C/A-code
• Highly stable external 10.23 MHz oscillator
• Clock division to obtain 1.023 MHz clock
• 10 bit LFSR with a 1023 chip length
• Internal setup for satellite selection
• FPGA implementation
• Signal displaed on digital oscilloscope

17
GPS C/A Code Generator

External 10.23MHz clock input
1/10 frequency divider
1.023MHz clock output
10 bit LFSR
10 bit LFSR
datain
clock
testerout
digital oscilloscope

• Block diagram of C/A code generator design

18
GPS Signal Generator
19
P-Code Generator
20
Virtex FPGA
21
Nallatech Board
22
GPS Signal Acquisition
Al_Aqeeli, Abdulqadir
Nallatechs Virtex Board
ICS-Card ADC
Analog GPS signal
8MHz (up to 50MHz) 12-bit Samples
8MHz 12-bit Samples
PCI Bus Max 33MHz
The samples go to the Hard Drive for storage and
to the Virtex Board for real-time processing
Hard Drive
23
Code Phase Search(n search bins)
Shift0
Incoming Code
Shift1
Shiftm
Shiftn-1
24
Walsh Transform(WT) Based Correlator
WT and PN codes are permutationally similar

• Only one transform is required
• nlog(n) real additions (or subtractions).

25
Permutations Generator
for simplicity, example of 3bit PN code is shown
26
Walsh Transform
 
 
X0
Y0
 
 
Y1
X1
 
 
X2
Y2
 
 
Y3
X3
   
Positive Connection Negative Connection
27
1024-Point Walsh Transform

• Impossible to build a completely parallel
  architecture for 1024-point WT.
• Why? (I/O pins, silicon (or logic) area)
• Partition 1024 butterfly into smaller
  butterflies. (parallel arch. for small butterfly)
• 64 blocks of these 32-point WTs

28
Implementation of WT-Based PN Correlator
RAM
RAM
32-point WT
32-point WT
Incoming samples
Peak-search circuit
controllers
29
Design Performance

• silicon area (60 of Virtex FPGA)
• New code phase every 3 code periods.
• Max. Freq. 96MHz
• 20 times faster than FFT-based arch.
• WT hardware correlator is 2500 times faster than
  WT software correlator.

This can be up to 600 times faster if current
design modifications work successfully
30
Modeling and Test of Mixed Systems with Embedded
Software
Liu Dong

• Objective - build a behavioral model for WSV
  consisting of
• ? Analog parts
• Probe/Time-Base/Trigger Generator/Frequency
  Counter
• ? Digital Parts
• PLD Controller for Probe/Time-base/Frequency
  Counter
• ? Software
• Real C/C programs for PLD controller used as
  input variables to the behavioral model.
• ? Interfaces
•      between analog/digital parts, digital
  parts/software

31
Behavioral Modeling of Analog Parts

• Selected SABER from ANALOGY Inc. as
  Model-Build and Simulation Package for analog
  parts of the system
• Particular tasks
• ? Integrate design, modeling, simulation, and
  analysis into one platform throughout the whole
  process
• ? Provide interface with SPICE/MATLAB programs
• ? Use Hardware Description Language MAST for
  mixed-signal circuits
• ? Run a simulation that contains behavioral and
  transistor level component simultaneously.

32
Silicon Board after 2005
0.1µm , 200M Transistors
RF? / Analog
www
20 Mbyte Distributed Memory
200 32 Bit ASPPs
200MHz
reconfigurable interconnect
Image Speech Data Gesture
50 GIPS-500GOPS
More than IP assembly!!
33
System Design and IP
UML cC, JAVA MATLAB
System specs -gt Software
Global System Thinking
Source DeMan (ISSCC99)
34
CAD Tools for Circuit Analysis and Test

• Mixed signal and mixed mode system analysis
• C program to generate system equations
• Small sensitivity analysis and fault testing
• Ambiguity group partition
• Large sensitivity analysis
• Catastrophic fault detection

35
Time Sampling
Woodbury formula in matrix theory
36
Test Equation

• Single measurement node of single excitations

• The same measurement node of different
  locations of the same excitations

Test equation relates the limited measured
circuit responses with the faults in a linear way!
37
Fault Diagnosis

• Fault Detection Different measured results on
  fault-free and
• faulty circuit
  indicates faults detected.
• Idea of Fault Location find out which columns
  in a known
• 
  coefficient matrix satisfy the test equation
• Problem of fault location is transformed into
  math problem
• Locate the minimum size ambiguity group

38
Filter Example Circuit
39
Resistive Example Circuit
Model of OP AMP
20 nodes, 42 parameters, and 2 faulty parameters
R6, R26 7 voltage measurements on node 2 J
is applied between ground and node 2, 5, 7, 8 ,
11, 17, 19 respectively n19, p42, f2, m7,
f1ltmltp
40
Fault Detection
Assume R6 and R26 deviates as left, measure nodal
voltage of node 2 for the CUT and corresponding
fault-free circuit
Non-zero vector of measured deviations between
fault-free circuit and CUT indicates that at
least one faults is detected by the given
measurements.
41
Fault Location

• Summary of ambiguity locating technique
• Gaussian elimination ? any independent set
  will dependent
• on the measurement deviation vector
• QR factorization ? find the linear
  combination matrix
• Theorem and Lemmas ? locate the suspicious
  faulty groups
• Swapping performance ? reduce the size of the
  qualified
• ambiguity groups
• The ambiguity group with minimum size is
• concluded as the solution the fault location!

42
CAD Tools for Circuit Analysis and Test

• Block diagram of my program MASTA (mixed-mode
  ambiguous system testability analysis program)

43
Neural Network Data Classification

• Concept of Logic Brain
• Random learning data generation
• Multiple space classification of data
• Feature function extraction
• Dynamic selectivity strategy
• Training procedure for data identification
• FPGA implementation for fast training process

44
Clustering for Classification of HRR Signals

• Zeng, Yujing

45
Sample of Clustering Results
46
Cluster Growth Program
47
Distribution of MD and AMD
48
Threshold Ratio MinDistance
49
Comparison with k-means clustering
On Iris data 95 correct classification vs. 90
for k-means
50
Application to Image Segmentation
51
Application to Image Segmentation
Segmentation Result by Centroidlinkage ( err
11.72/pix, 263 regions)
Segmentation Result by Clustering ( err
6.57/pix, 282 regions)
52
Application to Image Segmentation
Segmentation Result by Centroidlinkage ( err
7.23/pix, 648 regions)
Segmentation Result by Clustering ( err
6.57/pix, 282 regions)
53
Future Work

• Extending the clustering program to higher
  dimensions
• Finding the preprocessing suitable for the
  clustering program
• Developing hierarchical clustering program based
  on the current approach
• Improving the estimate of the thresholds used
  in the cluster growth program and the merging
  program

54
Rough Sets vs Fuzzy Sets

• Nelson, Dale

Fuzzy Sets - How gray is the pixel
Rough Sets - How big is the pixel
55
High Range Resolution Radar
TRANSMITTED
WAVEFORM
UNKNOWN
AIRCRAFT
WAVEFORM
REFLECTED
0
1
TIME
56
HRR Signals on Two Targets
57
Partition the Signal
Interleave Partitioning
58
Why Use a Wavelet Transform?
59
Binary Multi-Class Labeling
60
Weighting Formula
61
Classification Results
62
Results Testing
63
Rough Set Theoretic HRR ATR
APPLICATIONS -1-D Signals -HRR -LADAR
vibration -Sonar -Medical -Stock
market -Data Mining
BREAKTHROUGHS -Reduct (classifier) generation
time from exponential to quadratic ! -Fusion of
marginal (poor performing) reducts -Wavelet
Transform Aiding -Multi partition to increase
number of range bins considered -Use of binary
multi-class entropy labeling -Entropy based range
bin selection -Performance within 1 of theoretic
best -Max problem size increased by 2 orders of
magnitude
METHOD -Normalize Signal -Partition Signal -
Block - Interleave -Wavelet Transform -Binary
Multi-class Entropy Labeling -Entropy based
Range Bin Selection -Determine Minimal
Reducts -Fuse marginal reducts for classification
Exponential
Quadratic
64
Design of Self-Organizing Neural Network
Jing Liang, Mingwei Ding, Yongtao Guo
65
Analog CounterLiang Jing
66
Analysis of the Operation
67
Mutual Information Principle
The entropy based mutual information is defined
as follows
where
and the differential entropy
Use a symmetrical function
68
Mutual Information Principle
Two approximation are used linear and
quadratic approximation
69
Mutual Information Learning
70
ENTROPY-BASED EVALUATOR
Yongtao Guo
71
Simulation Results
72
Hardware Implementation

• EBE hardware model
• Memory circuit (LUT)
• Comparator unit
• ECU
• Two registers

73
Hardware Implementation ECU Architecture
74
Synthesis Performance --Map design to Virtex
75
Synthesis Performance --FPGA Map
76
Synthesis Performance --Schematic
77
Synthesis Performance --FPGA Floorplan
Vendor Xilinx Family VIRTEX Device
V800BG432 Speed -4 Number of External GCLKIOBs
1 out of 4 25 Number of External
IOBs 47 out of 316 14 Number
of BLOCKRAMs 4 out of 28
14 Number of SLICEs 463
out of 9408 4 Number of DLLs
1 out of 4 25 Number of
GCLKs 1 out of 4
25 Number of TBUFs
256 out of 9632 2 Number of flip-flops
336 Minimum period
24.838ns Maximum frequency
40.261MHz Total equivalent gate
count for design 88,186 Additional JTAG gate
count for IOBs 2,304
78
System-on-a-Chip for future mobile terminals
Alsolaim, Ahamd
79
DReAM Architecture
Processing Plane
Communication Plane
Control Plane
Configuration Plane
I/O Plane
80
DReAM Architecture
81
Block diagram of the RPU
82
Performance of all the RPU

? Depends on the difference between the operands.
83
Matlab simulation environment
Scrambling code
QPSK Modulation
Walsh Code
84
Recent Projects Supported by Sarnoff
Behavioral Model of Intel 8031 Phillip
Southard Design of Pass Transistor VLSI Cell
Library Tao Lin, Phillip Southard
85
Behavioral Model of Intel 8031
Phillip Southard

• Intel 8031 with 8-bit CPU, 64K Data Memory
  Space
• 128 bytes of on-chip Data RAM
• 32 bi-directional/individually addressable I/O
  lines
• 2 16-bit timer/counters
• 6-source/5-vector interrupt structure
• Synthesize the RTL and behavior model of Intel
  8031
• Xilinx FPGA implementation

86
Project Status

• Design process was demonstrated by using a subset
  of instructions from the 8031
• Process for modeling a microcontroller was
  successful.
• Testing completed with a hardware modeler
  verified that instructions were implemented
  correctly.

87
Design of Pass Transistor VLSI Cell Library
Tao Lin, Phillip Southard
The purpose is to generate a PTL library
comparable to the general CMOS library and
examine the possibility of using PTL in the
top-down design.
88
Advantages of the PTL
1. Pass-transistor logic (PTL) has extremely
simple basic cell which can generate all logic
functions
2. NMOS based pass-transistor circuits have a
great potential to surpass the CMOS not only in
performance but also in area and power.
89
BDD in PTL Design
F
Fabcbdcd
90
Example MUX2 in PTL
CMOS (12 transistors)
PTL (7 transistors)
91
CMOS and PTL Layouts
CMOS
46 x 80 3680
PTL
37.5 x 80 3000