GOL In Lab System Test

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GOL In Lab System Test

• Physics Department, SMU
• Annie Xiang
• Summer, 2006

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List of Tests

• BERT part1
• Jitter test part1
• Jitter test part2
• BERT part2
• Power budget, power up

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BERT part1

• 40MHz_at_Tx, 32bits
• 80MHz_at_Rx, 16bits
• Feed counter data
• Electrical/optical error free
• Error injection successful
• Done

4
Jitter test part1

• Frame clock to serial data jitter
• GOL allowable p-p jitter on clkLHC 100ps
• Crystal Jitter, 1ps RMS spec
• Real time oscilloscope software pack worked (use
  golden pll, no filter, TJ_at_BERe-12)
• Crystal jitter 8ps measured
• GOL Comma data jitter 5ps

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Jitter test part1
XO clk
Smaller RJ Larger DJ Smaller TJ
GOL Serial Data
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Jitter test part1
XO clk
GOL Serial Data
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Jitter test part1
XO clk
GOL Serial Data
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Jitter test part1
XO clk
GOL Serial Data
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Jitter test part1
10
Jitter test part1
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Jitter test part2

• System Jitter tolerance
• TLK2501 as receiver

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BERT part2

• PRBS, HDL
• DIO access error count, Labview

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Power management

• Optical attenuation power budget
• Power up scheme - reliability

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10G serializer deserializer

• Max3952 with eval board
• Max3953 with eval board
• Serial data rate (10GbE LAN/WAN)
  9.953Gbps/10.3125Gbps
• 1/16 or 1/64 PLL, 1/16 clock recovery
• 16x4 FIFO buffer mux, 1/16 demux

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10G serializer deserializer

• Reference clock 155MHz/161MHz, 622MHz/644MHz
  LVDS
• Clock, parallel data LVDS, serial data CML
• Serializer 27-1 PRBS mode
• Deserializer loss of lock, loss of sync

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10G serializer deserializer