Physical Layer for the Specknet Design and Implementation

1
Physical Layer for the Specknet Design and
Implementation

• Louise Crockett
• University of Strathclyde
• louise.crockett_at_eee.strath.ac.uk

2
Summary

• Context
• Transmitter
• Design Flow
• Simulation, Implementation and Testing
• Further Developments
• Conclusions

3
Physical Layer
Network Layers
Physical Layer DSP
RF Section

• Zigbee chosen as demonstration platform
• Development of prototype
• Gained design experience
• Resolved some practical problems
• Ultimate Physical Layer design may be simpler
  than Zigbee

4
Context of Physical Layer

• Digital signal processing of data for
  transmission, and data received
• Simple protocol chosen for initial implementation
  
• 802.15.4 (Zigbee)
• Zigbee specifies
• Maximum data rate 250kb/s
• Half Sine pulse shaping
• Provides a basis for development

Higher Layers
Physical Layer
RF transmit / receive
5
Development system aims

• To design and implement a prototype physical
  layer on FPGA
• To interface with RF section
• To test performance and hardware requirements,
  and improve and optimise where possible
• To aid in creating a channel model for further
  development
• To create IP blocks which can be integrated with
  MAC and network layers onto a single FPGA

Air interface
DAC
RF
DAC
RF
FPGA
FPGA
Transmit side
Receive side
6
Transmitter detail

• Data rates shown are for Zigbee may be reduced
  in proportion

250 kb/s
Transmit Filter I Phase
Binary data
Bit to symbol mapping
1 Mchip/s
Transmit Filter Q Phase
b3
b2
b1
b0
I phase
62.5 kbaud
Symbol to chip mapping
Offset QPSK mapping
Q phase
1 Mchip/s
2 Mchip/s
7
Design Flow
High level simulation
VHDL design entry
Test vectors
Simulation
Synthesis
RTL Netlist
Place and Route
User Constraints File
Reports, Floorplan etc.
Download to FPGA
Oscilloscope probe
8
Simulation results

• Active HDL simulator used to verify output

9
Synthesis

• Synplify Pro was used as the synthesis tool
• A netlist is created from the VHDL source
• This is the main input to the Place and Route
  stage
• It can also be used to visualise the design

10
Implementation

• Xilinx ISE was used to target the Spartan II FPGA
  on board the Nallatech Strathnuey development
  board
• 150,000 gates on User FPGA
• A User Constraints File was created
• Maps output signals to pins
• Applies timing constraints
• Various reports available
• Timing analysis (constraints met)
• Hardware usage ( 5)
• Floorplan showing placement

11
Floorplan
LED outputs
Bit to Symbol
Internal Clock division
Symbol to chip OQPSK modulation
Q Filter
SNDACINF
External Clock division
I Filter
Clock inputs
DAC outputs
12
On-board Testing

• For testing, a wrapper had to be created around
  the transmitter entity. Included
• Test vectors,
• Formatting of I and Q outputs for DAC
• SNDACINF entity to interface with on-board DAC
• Mapping of selected outputs to on-board LEDs

Test Vectors
Format I
LED array
Format Q
Zigbee Transmitter
SNDACINF
Clock division
DAC
Oscilloscope
13
Test setup

• Nallatechs Fuse software was used to interface
  between the computer and FPGA
• An oscilloscope was used to probe the outputs of
  the DAC
• This verified the design and the operation of the
  DAC

14
Further Developments I

• Some modifications to the design are necessary
• Migrate from Strathnuey to Xtreme DSP Kit to
  allow faster DAC to be used
• Several MHz, rather than 400kHz output
• Combine I and Q phases to provide single output
• Requires more sophisticated filtering
• Continue working closely with University of
  Glasgow to interface with RF section of design
• Evaluation and improvement of pulse shaping stage
• Improved communications between PC and FPGA

15
Further Developments II - Receiver

• Starting from a higher level of abstraction
• SystemView with FXPlib (Fixed Point Library)
• More detailed analysis of effects of short
  wordlengths
• New challenges
• Synchronisation
• Channel estimation
• Aiming for completion by Christmas 2004

16
Conclusions

• Working Zigbee-based transmitter designed,
  implemented and tested on FPGA
• Some minor modifications required
• Design allows for experimentation with pulse
  shapes, chipping sequences etc.
• Next stage receiver!

17
Review

• Transmitter in detail
• Design flow
• Inputs and outputs
• Simulation, implementation and testing
• Simulation and on-chip test results
• Detailed next stages of work
• Experimentation with filters etc.
• Receiver
• Integration with RF