BASIC COMPUTER ORGANIZATION AND DESIGN

1
BASIC COMPUTER ORGANIZATION AND DESIGN
Instruction Codes Computer Registers
Computer Instructions Timing and Control
Instruction Cycle Memory Reference
Instructions Input-Output and Interrupt
Complete Computer Description Design of Basic
Computer Design of Accumulator Logic
2
INTRODUCTION

• Every different processor type has its own design
  (different registers, buses, microoperations,
  machine instructions, etc)
• Modern processor is a very complex device
• It contains
• Many registers
• Multiple arithmetic units, for both integer and
  floating point calculations
• The ability to pipeline several consecutive
  instructions to speed execution
• Etc.
• However, to understand how processors work, we
  will start with a simplified processor model
• This is similar to what real processors were like
  25 years ago
• M. Morris Mano introduces a simple processor
  model he calls the Basic Computer
• We will use this to introduce processor
  organization and the relationship of the RTL
  model to the higher level computer processor

3
THE BASIC COMPUTER

• The Basic Computer has two components, a
  processor and memory
• The memory has 4096 words in it
• 4096 212, so it takes 12 bits to select a word
  in memory
• Each word is 16 bits long

CPU
RAM
0
0
15
4095
4
INSTRUCTIONS
Instruction codes

• Program
• A sequence of (machine) instructions
• (Machine) Instruction
• A group of bits that tell the computer to perform
  a specific operation (a sequence of
  micro-operation)
• The instructions of a program, along with any
  needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates
  the instruction into the sequence of
  microoperations necessary to implement it

5
INSTRUCTION FORMAT
Instruction codes

• A computer instruction is often divided into two
  parts
• An opcode (Operation Code) that specifies the
  operation for that instruction
• An address that specifies the registers and/or
  locations in memory to use for that operation
• In the Basic Computer, since the memory contains
  4096 ( 212) words, we needs 12 bit to specify
  which memory address this instruction will use
• In the Basic Computer, bit 15 of the instruction
  specifies the addressing mode (0 direct
  addressing, 1 indirect addressing)
• Since the memory words, and hence the
  instructions, are 16 bits long, that leaves 3
  bits for the instructions opcode

6
ADDRESSING MODES
Instruction codes

• The address field of an instruction can represent
  either
• Direct address the address in memory of the data
  to use (the address of the operand), or
• Indirect address the address in memory of the
  address in memory of the data to use
• Effective Address (EA)
• The address, that can be directly used without
  modification to access an operand for a
  computation-type instruction, or as the target
  address for a branch-type instruction

7
PROCESSOR REGISTERS
Instruction codes

• A processor has many registers to hold
  instructions, addresses, data, etc
• The processor has a register, the Program Counter
  (PC) that holds the memory address of the next
  instruction to get
• Since the memory in the Basic Computer only has
  4096 locations, the PC only needs 12 bits
• In a direct or indirect addressing, the processor
  needs to keep track of what locations in memory
  it is addressing The Address Register (AR) is
  used for this
• The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or
  indirect addressing, it is placed in the Data
  Register (DR). The processor then uses this value
  as data for its operation
• The Basic Computer has a single general purpose
  register the Accumulator (AC)

8
PROCESSOR REGISTERS
Instruction codes

• The significance of a general purpose register is
  that it can be referred to in instructions
• e.g. load AC with the contents of a specific
  memory location store the contents of AC into a
  specified memory location
• Often a processor will need a scratch register to
  store intermediate results or other temporary
  data in the Basic Computer this is the Temporary
  Register (TR)
• The Basic Computer uses a very simple model of
  input/output (I/O) operations
• Input devices are considered to send 8 bits of
  character data to the processor
• The processor can send 8 bits of character data
  to output devices
• The Input Register (INPR) holds an 8 bit
  character gotten from an input device
• The Output Register (OUTR) holds an 8 bit
  character to be send to an output device

9
BASIC COMPUTER REGISTERS
Registers
Registers in the Basic Computer
11
0
PC
Memory
11
0
4096 x 16
AR

15
0
IR
CPU
15
0
15
0
TR
DR
7
0
0
7
15
0
OUTR
AC
INPR
List of BC Registers
DR 16 Data Register Holds
memory operand AR 12 Address
Register Holds address for memory AC
16 Accumulator Processor
register IR 16 Instruction
Register Holds instruction code PC
12 Program Counter Holds address of
instruction TR 16 Temporary
Register Holds temporary data INPR 8
Input Register Holds input
character OUTR 8 Output Register
Holds output character
10
COMMON BUS SYSTEM
Registers

• The registers in the Basic Computer are connected
  using a bus
• This gives a savings in circuitry over complete
  connections between registers

11
COMMON BUS SYSTEM
Registers
S2
S1
Bus
S0
Memory unit
7
4096 x 16
Address
Read
Write
AR
1
LD INR CLR
PC
2
LD INR CLR
DR
3
LD INR CLR
E

AC
4
ALU
LD INR CLR
INPR
IR
5
LD
TR
6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
12
COMMON BUS SYSTEM
Registers
S0
S1
S2
13
COMMON BUS SYSTEM
Registers

• Three control lines, S2, S1, and S0 control which
  register the bus selects as its input
• Either one of the registers will have its load
  signal activated, or the memory will have its
  read signal activated
• Will determine where the data from the bus gets
  loaded
• The 12-bit registers, AR and PC, have 0s loaded
  onto the bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the
  bus, the data comes from the low order 8 bits on
  the bus

S2 S1 S0 Register
0 0 0 x 0 0 1 AR 0 1 0 PC 0 1
1 DR 1 0 0 AC 1 0 1 IR 1 1 0 TR 1 1
1 Memory
14
BASIC COMPUTER INSTRUCTIONS
Instructions

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code 000
110)
15 14
12 11
0
Opcode
Address
I
Register-Reference Instructions (OP-code 111,
I 0)
Input-Output Instructions (OP-code 111, I 1)
15
BASIC COMPUTER INSTRUCTIONS
Instructions
Hex Code Symbol I 0
I 1 Description
AND 0xxx 8xxx AND memory word to
AC ADD 1xxx 9xxx Add memory word
to AC LDA 2xxx Axxx Load AC from
memory STA 3xxx Bxxx Store
content of AC into memory BUN 4xxx
Cxxx Branch unconditionally BSA 5xxx
Dxxx Branch and save return address ISZ
6xxx Exxx Increment and skip
if zero CLA 7800 Clear AC CLE
7400 Clear E CMA 7200
Complement AC CME 7100 Complement
E CIR 7080 Circulate right AC and
E CIL 7040 Circulate left AC and
E INC 7020 Increment AC SPA 7010
Skip next instr. if AC is positive SNA
7008 Skip next instr. if AC is
negative SZA 7004 Skip next instr.
if AC is zero SZE 7002 Skip next
instr. if E is zero HLT 7001 Halt
computer INP F800 Input character
to AC OUT F400 Output character from
AC SKI F200 Skip on
input flag SKO F100 Skip on output
flag ION F080 Interrupt on IOF
F040 Interrupt off
16
INSTRUCTION SET COMPLETENESS
Instructions
A computer should have a set of instructions so
that the user can construct machine language
programs to evaluate any function that is known
to be computable.

• Instruction Types

Functional Instructions - Arithmetic,
logic, and shift instructions - ADD, CMA,
INC, CIR, CIL, AND, CLA Transfer Instructions
- Data transfers between the main memory and
the processor registers - LDA, STA Control
Instructions - Program sequencing and
control - BUN, BSA, ISZ Input/Output
Instructions - Input and output -
INP, OUT
17
CONTROL UNIT
Instruction codes

• Control unit (CU) of a processor translates from
  machine instructions to the control signals for
  the microoperations that implement them
• Control units are implemented in one of two ways
• Hardwired Control
• CU is made up of sequential and combinational
  circuits to generate the control signals
• Microprogrammed Control
• A control memory on the processor contains
  microprograms that activate the necessary control
  signals
• We will consider a hardwired implementation of
  the control unit for the Basic Computer

18
TIMING AND CONTROL
Timing and control
Control unit of Basic Computer
Instruction register (IR)
15
14 13 12
11 - 0
Other inputs
3 x 8
decoder
7 6 5 4 3 2 1 0
D
0
Combinational Control logic
I
Control signals
D
7
T
15
T
0
15 14 . . . . 2 1 0
4 x 16
decoder
Increment (INR)
4-bit
sequence
Clear (CLR)
counter
Clock
(SC)
19
TIMING SIGNALS
Timing and control
- Generated by 4-bit sequence counter and 4?16
decoder - The SC can be incremented or
cleared. - Example T0, T1, T2, T3, T4, T0,
T1, . . . Assume At time T4, SC is
cleared to 0 if decoder output D3 is active.
D3T4 SC ? 0
20
INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is
  executed in the following cycle
• Fetch an instruction from memory
• Decode the instruction
• Read the effective address from memory if the
  instruction has an indirect address
• Execute the instruction
• After an instruction is executed, the cycle
  starts again at step 1, for the next instruction
• Note Every different processor has its own
  (different) instruction cycle

21
FETCH and DECODE
Instruction Cycle
Fetch and Decode
T0 AR ??PC (S0S1S2010, T01) T1 IR ? M AR,
PC ? PC 1 (S0S1S2111, T11) T2 D0, . . . ,
D7 ? Decode IR(12-14), AR ? IR(0-11), I ? IR(15)
T1
S2
Bus
T0
S1
S0
Memory
7
unit
Address
Read
AR
1
LD
PC
2
INR
IR
5
LD
Clock
Common bus
22
DETERMINE THE TYPE OF INSTRUCTION
Instrction Cycle
Start SC ? 0
T0
AR
?
PC
T1
IR
?
MAR,
PC
?
PC 1
T2
Decode Opcode in IR(12-14),
?
AR
?
IR(0-11),
I
IR(15)
0 (Memory-reference)
(Register or I/O) 1
D7
0 (direct)
(I/O) 1
0 (register)
(indirect) 1
I
I
T3
T3
T3
T3
Nothing
Execute
Execute
MAR
?
AR
register-reference
input-output
instruction
instruction
SC
?
0
SC
?
0
Execute
T4
memory-reference
instruction
SC
?
0
D'7IT3 AR ??MAR D'7I'T3 Nothing D7I'T3 Execut
e a register-reference instr. D7IT3 Execute an
input-output instr.
23
REGISTER REFERENCE INSTRUCTIONS
Instruction Cycle
Register Reference Instructions are identified
when
- D7 1, I 0 - Register Ref. Instr. is
specified in b0 b11 of IR - Execution starts
with timing signal T3
r D7 I?T3 gt Register Reference
Instruction Bi IR(i) , i0,1,2,...,11

r SC ? 0 CLA rB11 AC ? 0 CLE rB10 E ?
0 CMA rB9 AC ? AC CME rB8 E ?
E CIR rB7 AC ? shr AC, AC(15) ? E, E ?
AC(0) CIL rB6 AC ? shl AC, AC(0) ? E, E ?
AC(15) INC rB5 AC ? AC 1 SPA rB4 if (AC(15)
0) then (PC ? PC1) SNA rB3 if (AC(15) 1)
then (PC ? PC1) SZA rB2 if (AC 0) then (PC ?
PC1) SZE rB1 if (E 0) then (PC ?
PC1) HLT rB0 S ? 0 (S is a start-stop
flip-flop)
24
MEMORY REFERENCE INSTRUCTIONS
MR Instructions
Operation Decoder
Symbol
Symbolic Description
AND D0 AC ? AC ? MAR ADD D1 AC ? AC
MAR, E ? Cout LDA D2 AC ? MAR STA
D3 MAR ? AC BUN D4 PC ? AR BSA
D5 MAR ? PC, PC ? AR 1 ISZ D6 MAR
? MAR 1, if MAR 1 0 then PC ? PC1
- The effective address of the instruction is in
AR and was placed there during timing signal T2
when I 0, or during timing signal T3 when I
1 - Memory cycle is assumed to be short enough to
complete in a CPU cycle - The execution of MR
instruction starts with T4
AND to AC D0T4 DR ? MAR Read
operand D0T5 AC ? AC ? DR, SC ? 0 AND with
AC ADD to AC D1T4 DR ? MAR Read
operand D1T5 AC ? AC DR, E ? Cout, SC ? 0 Add
to AC and store carry in E
25
MEMORY REFERENCE INSTRUCTIONS
LDA Load to AC D2T4 DR ? MAR D2T5 AC ? DR,
SC ? 0 STA Store AC D3T4 MAR ? AC, SC ?
0 BUN Branch Unconditionally D4T4 PC ? AR, SC
? 0 BSA Branch and Save Return Address MAR ?
PC, PC ? AR 1
Memory, PC, AR at time T4
Memory, PC after execution
0
BSA
135
20
0
BSA
135
20
PC 21
Next instruction
Next instruction
21
AR 135
21
135
Subroutine
136
Subroutine
PC 136
1
BUN
135
1
BUN
135
Memory
Memory
26
MEMORY REFERENCE INSTRUCTIONS
MR Instructions
BSA D5T4 MAR ? PC, AR ? AR 1 D5T5 PC ?
AR, SC ? 0 ISZ Increment and Skip-if-Zero D6T4
DR ? MAR D6T5 DR ? DR 1 D6T4 MAR ? DR,
if (DR 0) then (PC ? PC 1), SC ? 0
27
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
MR Instructions
Memory-reference instruction
AND
ADD
LDA
STA
D T
D T
D T
D T
4
1
4
2
4
3
4
0
MAR ? AC
DR ? MAR
DR ? MAR
DR ? MAR
SC ? 0
D T
D T
D T
0
5
1
5
2
5
?
AC ? AC DR
AC ? DR
AC ? AC DR
SC ? 0
SC ? 0
E ? Cout
SC ? 0
BUN
BSA
ISZ
D T
D T
D T
4
4
5
4
6
4
PC ? AR
MAR ? PC
DR ? MAR
SC ? 0
AR ? AR 1
D T
D T
5
5
6
5
DR ? DR 1
PC ? AR
SC ? 0
D T
6
6
MAR ? DR
If (DR 0)
then (PC ? PC 1)
SC ? 0
28
INPUT-OUTPUT AND INTERRUPT
I/O and Interrupt
A Terminal with a keyboard and a Printer

• Input-Output Configuration

Serial
Computer registers and flip-flops
Input-output
communication
terminal
interface
Receiver
Printer
FGO
OUTR
interface
AC
Transmitter
Keyboard
INPR
FGI
interface
INPR Input register - 8 bits OUTR Output register
- 8 bits FGI Input flag - 1 bit FGO Output flag -
1 bit IEN Interrupt enable - 1 bit
Serial Communications Path
Parallel Communications Path
- The terminal sends and receives serial
information - The serial info. from the keyboard
is shifted into INPR - The serial info. for the
printer is stored in the OUTR - INPR and OUTR
communicate with the terminal serially and with
the AC in parallel. - The flags are needed to
synchronize the timing difference between
I/O device and the computer
29
PROGRAM CONTROLLED DATA TRANSFER
I/O and Interrupt
-- CPU --
-- I/O Device --
loop If FGI 1 goto loop INPR ? ?new
data, FGI ? 1 loop If FGO 1 goto loop
consume OUTR, FGO ? 1
/ Input / / Initially FGI 0 /
loop If FGI 0 goto loop AC ?
?INPR, FGI ? 0 / Output / /
Initially FGO 1 / loop If FGO 0 goto
loop OUTR ? ?AC, FGO ? 0
FGI0
FGO1
Start Input
Start Output
FGI ? 0
AC ? Data
yes
yes
FGI0
FGO0
no
no
AC ? INPR
OUTR ? AC
FGO ? 0
yes
More Character
More Character
yes
no
END
no
END
30
INPUT-OUTPUT INSTRUCTIONS
D7IT3 p IR(i) Bi, i 6, , 11
p SC ? 0 Clear SC INP pB11 AC(0-7) ? INPR,
FGI ? 0 Input char. to AC OUT pB10 OUTR ?
AC(0-7), FGO ? 0 Output char. from AC
SKI pB9 if(FGI 1) then (PC ? PC 1) Skip on
input flag SKO pB8 if(FGO 1) then (PC ? PC
1) Skip on output flag ION pB7 IEN ?
1 Interrupt enable on IOF pB6 IEN ?
0 Interrupt enable off
31
PROGRAM-CONTROLLED INPUT/OUTPUT
I/O and Interrupt

• Program-controlled I/O

- Continuous CPU involvement I/O
takes valuable CPU time - CPU slowed down to I/O
speed - Simple - Least hardware
Input LOOP, SKI DEV
BUN LOOP
INP DEV Output LOOP, LDA
DATA LOP, SKO DEV
BUN LOP
OUT DEV
32
INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to
be passed --gt interrupt. - The I/O interface,
instead of the CPU, monitors the I/O device. -
When the interface founds that the I/O device is
ready for data transfer, it generates an
interrupt request to the CPU - Upon detecting
an interrupt, the CPU stops momentarily the task
it is doing, branches to the service routine to
process the data transfer, and then returns to
the task it was performing.
IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions - when
cleared, the computer cannot be interrupted
33
FLOWCHART FOR INTERRUPT CYCLE
I/O and Interrupt
R Interrupt f/f
1
0
Interrupt cycle
Instruction cycle
R
Store return address
Fetch and decode
in location 0
instructions
M0 ? PC
0
Execute
IEN
instructions
Branch to location 1
1
PC ? 1
1
FGI
0
IEN ? 0 R ? 0
1
FGO
0
R ? 1
- The interrupt cycle is a HW implementation of a
branch and save return address operation. -
At the beginning of the next instruction cycle,
the instruction that is read from memory is
in address 1. - At memory address 1, the
programmer must store a branch instruction that
sends the control to an interrupt service
routine - The instruction that returns the
control to the original program is "indirect
BUN 0"

34
REGISTER TRANSFER OPERATIONS IN INTERRUPT
CYCLE
I/O and Interrupt
Memory
Before interrupt
After interrupt cycle
256
0
0
0
BUN
1120
1
0
BUN
1120
PC 1
Main
Main
255
Program
255
Program
PC 256
256
1120
1120
I/O
I/O
Program
Program
1
BUN
0
1
BUN
0
Register Transfer Statements for Interrupt
Cycle - R F/F ? 1 if IEN (FGI
FGO)T0?T1?T2? ? T0?T1?T2? (IEN)(FGI FGO)
R ? 1 - The fetch and decode phases of the
instruction cycle must be modified ?Replace
T0, T1, T2 with R'T0, R'T1, R'T2 - The
interrupt cycle RT0 AR ? 0, TR ?
PC RT1 MAR ? TR, PC ? 0 RT2 PC ? PC 1,
IEN ? 0, R ? 0, SC ? 0


35
FURTHER QUESTIONS ON INTERRUPT
I/O and Interrupt
How can the CPU recognize the device
requesting an interrupt ? Since different
devices are likely to require different
interrupt service routines, how can the CPU
obtain the starting address of the
appropriate routine in each case ? Should any
device be allowed to interrupt the CPU while
another interrupt is being serviced ? How can
the situation be handled when two or more
interrupt requests occur simultaneously ?
36
COMPLETE COMPUTER DESCRIPTIONFlowchart of
Operations
Description
start SC ? 0, IEN ? 0, R ? 0
0(Instruction 1(Interrupt
Cycle) Cycle)
R
RT0
RT0
AR ? 0, TR ? PC
AR ? PC
RT1
RT1
IR ? MAR, PC ? PC 1
MAR ? TR, PC ? 0
RT2
RT2
AR ? IR(011), I ? IR(15) D0...D7 ? Decode IR(12
14)
PC ? PC 1, IEN ? 0 R ? 0, SC ? 0
1(Register or I/O) 0(Memory Ref)
D7
1 (I/O) 0 (Register)
1(Indir) 0(Dir)
I
I
D7IT3 D7IT3
D7IT3 D7IT3
Execute RR Instruction
AR lt- MAR
Idle
Execute I/O Instruction
D7T4
Execute MR Instruction
37
COMPLETE COMPUTER DESCRIPTION
Microoperations
Description
Fetch Decode Indirect Interrupt
Memory-Reference AND
ADD LDA STA BUN BSA ISZ
R?T0 R?T1 R?T2 D7?IT3 RT0 RT1 RT2
D0T4 D0T5 D1T4 D1T5 D2T4 D2T5 D3T4 D4T4 D
5T4 D5T5 D6T4 D6T5 D6T6
AR ? PC IR ? MAR, PC ? PC 1 D0, ..., D7 ?
Decode IR(12 14), AR ? IR(0 11), I ?
IR(15) AR ? MAR R ? 1 AR ? 0, TR ? PC MAR ?
TR, PC ? 0 PC ? PC 1, IEN ? 0, R ? 0, SC ?
0 DR ? MAR AC ? AC ? DR, SC ? 0 DR ? MAR AC
? AC DR, E ? Cout, SC ? 0 DR ? MAR AC ? DR,
SC ? 0 MAR ? AC, SC ? 0 PC ? AR, SC ? 0 MAR ?
PC, AR ? AR 1 PC ? AR, SC ? 0 DR ? MAR DR ?
DR 1 MAR ? DR, if(DR0) then (PC ? PC 1),
SC ? 0
T0?T1?T2?(IEN)(FGI FGO)
38
COMPLETE COMPUTER DESCRIPTION
Microoperations
Description
Register-Reference CLA CLE CMA
CME CIR CIL INC SPA SNA
SZA SZE HLT Input-Output INP
OUT SKI SKO ION IOF
D7I?T3 r IR(i) Bi r rB11
rB10 rB9 rB8 rB7 rB6 rB5 rB4
rB3 rB2 rB1 rB0 D7IT3 p IR(i) Bi
p pB11 pB10 pB9 pB8
pB7 pB6
(Common to all register-reference instr) (i
0,1,2, ..., 11) SC ? 0 AC ? 0 E ? 0 AC ? AC? E ?
E? AC ? shr AC, AC(15) ? E, E ? AC(0) AC ? shl
AC, AC(0) ? E, E ? AC(15) AC ? AC 1 If(AC(15)
0) then (PC ? PC 1) If(AC(15) 1) then (PC ?
PC 1) If(AC 0) then (PC ? PC 1) If(E0)
then (PC ? PC 1) S ? 0 (Common to all
input-output instructions) (i 6,7,8,9,10,11) SC
? 0 AC(0-7) ? INPR, FGI ? 0 OUTR ? AC(0-7), FGO ?
0 If(FGI1) then (PC ? PC 1) If(FGO1) then (PC
? PC 1) IEN ? 1 IEN ? 0
39
DESIGN OF BASIC COMPUTER(BC)
Design of Basic Computer
Hardware Components of BC
A memory unit 4096 x 16. Registers
AR, PC, DR, AC, IR, TR, OUTR, INPR, and
SC Flip-Flops(Status) I, S, E, R,
IEN, FGI, and FGO Decoders a 3x8 Opcode
decoder a 4x16 timing
decoder Common bus 16 bits Control logic
gates Adder and Logic circuit Connected to AC
Control Logic Gates
- Input Controls of the nine registers - Read and
Write Controls of memory - Set, Clear, or
Complement Controls of the flip-flops - S2, S1,
S0 Controls to select a register for the bus -
AC, and Adder and Logic circuit
40
CONTROL OF REGISTERS AND MEMORY
Design of Basic Computer
Address Register AR
Scan all of the register transfer statements that
change the content of AR
RT0 AR ? PC LD(AR) RT2
AR ? IR(0-11) LD(AR) D7IT3 AR ? MAR
LD(AR) RT0 AR ? 0
CLR(AR) D5T4 AR ? AR 1 INR(AR)
LD(AR) R'T0 R'T2 D'7IT3 CLR(AR)
RT0 INR(AR) D5T4
41
CONTROL OF FLAGS
Design of Basic Computer
IEN Interrupt Enable Flag
pB7 IEN ? 1 (I/O Instruction) pB6 IEN ?
0 (I/O Instruction) RT2 IEN ? 0
(Interrupt) p D7IT3 (Input/Output Instruction)
42
CONTROL OF COMMON BUS
Design of Basic Computer
selected register
x1 x2 x3 x4 x5 x6 x7
S2 S1 S0
0 0 0 0 0 0 0 0 0
0 none 1 0 0 0 0 0 0
0 0 1 AR 0 1 0 0
0 0 0 0 1 0 PC 0
0 1 0 0 0 0 0 1 1
DR 0 0 0 1 0 0 0
1 0 0 AC 0 0 0 0 1
0 0 1 0 1 IR 0 0
0 0 0 1 0 1 1 0
TR 0 0 0 0 0 0 1 1
1 1 Memory
For AR
D4T4 PC ? AR D5T5 PC ? AR
x1 D4T4 D5T5
43
DESIGN OF ACCUMULATOR LOGIC
Design of AC Logic
Circuits associated with AC
All the statements that change the content of AC
D0T5 AC ? AC ? DR AND with DR D1T5 AC ?
AC DR Add with DR D2T5 AC ? DR
Transfer from DR pB11 AC(0-7) ? INPR
Transfer from INPR rB9 AC ? AC?
Complement rB7 AC ? shr AC, AC(15) ? E Shift
right rB6 AC ? shl AC, AC(0) ? E Shift
left rB11 AC ? 0 Clear rB5 AC ? AC
1 Increment
44
CONTROL OF AC REGISTER
Design of AC Logic
Gate structures for controlling the LD, INR, and
CLR of AC
45
ALU (ADDER AND LOGIC CIRCUIT)
Design of AC Logic
One stage of Adder and Logic circuit