EE365 - PowerPoint PPT Presentation

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EE365

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Parity computation. Used to generate and check parity bits in computer systems. ... Parity tree. Faster with balanced tree structure. 37. Next time. Comparators ... – PowerPoint PPT presentation

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Title: EE365


1
EE365
  • Three-state Outputs
  • Encoders
  • Multiplexers
  • XOR gates

2
Three-state buffers
  • Output LOW, HIGH, or Hi-Z.
  • Can tie multiple outputs together, if at most one
    at a time is driven.

3
Different flavors
4
(No Transcript)
5
Timing considerations
6
Three-state drivers
7
Driver application
8
Three-state transceiver
9
Transceiver application
10
Encoders vs. Decoders
11
Binary encoders
12
Need priority in most applications
13
8-input priority encoder
14
Priority-encoder logic equations
15
74x148 8-input priority encoder
  • Active-low I/O
  • Enable Input
  • Got Something
  • Enable Output

16
74x148circuit
17
74x148 Truth Table
18
Cascading priority encoders
  • 32-inputpriority encoder

19
Constant expressions
20
Outputs
21
Alternative formulation
  • WHEN is very natural for priority function

22
Multiplexers
23
74x1518-input multiplexer
24
74x151 truth table
25
CMOS transmission gates
  • 2-input multiplexer

26
Other multiplexer varieties
  • 2-input, 4-bit-wide
  • 74x157
  • 4-input, 2-bit-wide
  • 74x153

27
Barrel shifter design example
  • n data inputs, n data outputs
  • Control inputs specify number of positions to
    rotate or shift data inputs
  • Example n 16
  • DIN150, DOUT150, S30 (shift amount)
  • Many possible solutions, all based on multiplexers

28
16 16-to-1 muxes
16-to-1 mux 2 x 74x151 8-to-1 mux NAND gate
29
4 16-bit 2-to-1 muxes
16-bit 2-to-1 mux 4 x 74x157 4-bit 2-to-1 mux
30
Properties of different approaches
31
2-input XOR gates
  • Like an OR gate, but excludes the case where both
    inputs are 1.
  • XNOR complement of XOR

32
XOR and XNOR symbols
33
Gate-level XOR circuits
  • No direct realization with just a few transistors.

34
CMOS XOR with transmission gates
IF B1 THEN Z !A ELSE Z A
35
Multi-input XOR
  • Sum modulo 2
  • Parity computation
  • Used to generate and check parity bits in
    computer systems.
  • Detects any single-bit error

36
Parity tree
  • Faster with balanced tree structure

37
Next time
  • Comparators
  • Adders
  • Multipliers
  • Read-only memories (ROMs)
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