HST SM-4 Relative Navigation Sensor (RNS) Xilinx Applications

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HST SM-4 Relative Navigation Sensor (RNS)Xilinx
Applications

• Ray Bietry
• NASA, Goddard Space Flight Center
• Orbital Sciences Corporation
• June 5, 2007

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RNS Mission Objectives

• Camera survey of Soft Capture Mechanism after
  installation on HST Aft Bulkhead
• Advance TRL of critical, high risk automated
  rendezvous and docking (ARD) technologies
  (sensors, image processing, relative state
  estimation) at low risk and impact to SM4 (HST
  and Shuttle Program)
• Risk reduction for eventual (non-Shuttle) return
  to HST
• Enhances NASA ARD capabilities beyond HST
  application
• SM-4 mission success is not a function of RNS

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RNS Rendezvous Timeline
RNS Record TI 35 min
Grapple Sunset 3 min
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Baseline RNS Data Flow
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HST Rendezvous
RNS Ops
RNS Ops
Camera GPS Record
GPS Record
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Camera Views
120gate
RNS 1
GRAPPLE
HOVER
RNS 3
RNS 2
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RNS 2 FoV Study

• 1000x1000 pixel image
• FOV 23 F 2.8
• Distance from camera to center of aft bulkhead
  23 m
• HST translating from 120 ft gate to grapple
  position

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RNS 3 FoV Study

• 1000x1000 pixel image
• FOV 23
• Distance from camera to center of aft bulkhead
  90.2 in / 2.29 m
• HST in FSS HOVER position
• BAPS Latch in lower field of view

BAPS Latch
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How ULTOR Works
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NFIR Algorithm Description

• Model effectively a wire frame delineating the
  coordinates of vehicle (HST) features expected to
  be readily recognizable in the video images.
• Readily recognizable implies detectable through
  use of an edge detection algorithm under the
  expected lighting conditions.
• NFIR uses the Pose, model points (3D), matched
  image points (2D) to estimate the motion between
  frames. This motion is applied to the Pose to
  obtain the estimated Pose.

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SM4 Payload Bay Configuration
RNS Cameras
MULE
FSS
ORUC
SLIC
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MULE Configuration
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Mechanical Interfaces -RNS Avionics Plate
Navigator GPS Receiver
SpaceCube
ICE
Connector Bracket
RNS Avionics Plate
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Mechanical Interfaces -RNS Camera Mounting
Forward
Starboard
Overall View of RNS Cameras to MULE
Mounting Camera to MULE Interfaces defined in
RNS to MULE ICD (GE 2098605)
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RNS Architecture Enhanced Configuration
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ICE Telemetry Module

• The Hubble Space Telescope Project regularly
  flies new components to the observatory on Space
  Shuttle Carriers.
• The Telemetry Module is reconfigurable and
  flexible with the use of reprogrammable FPGAs
  from Xilinx (Virtex series).
• Three redundant Xilinx FPGAs (XFPGA) with one
  non-reprogrammable Actel FGPA (AFPGA).
• AFPGA votes on the outputs of the three XFPGA to
  mitigate SEU events.
• XFPGAs contain core avionics functions.

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Telemetry Module Architecture
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Embedded Processor

• VHDL source code is available for various
  microcontrollers.
• HST currently owns COTS software tools (C
  compilers and assemblers) for 8051 and Microchip
  PIC CPUs.
• VHDL source code obtained for a microcontroller
  compliant with the Microchip PIC 16 instruction
  set (35 instruction, RISC architecture)
• Modifications made to the VHDL to add a UART,
  block RAM access, and an application-specific bus
  interface.

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PSP Command Interface

• Conforms to ICD-19001 PSP Shuttle Interface.
• Data stream is 16kHz carrier with 180 degree
  phase change.
• Simple interface circuit consists of 422
  receiver and discrete components.
• Allows analog or digital PSK stream.
• High sensitivity and dynamic range. 1 - 15 Vp-p
  input voltage range.
• 3 to 4.5Vp-p required.
• Can use differential or single-ended source.
• Data presented byte-wide to Microprocessor in
  FIFO.
• Minimizes processor work load.

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PSP Command Decoder
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Configuration Scrubber

• Configuration Scrubber consists of 2 subsystems
• Readback Compare
• Configure

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Configuration Scrubber

• Readback Compare
• Reads all 3 Virtex FPGAs, simultaneously compares
  configuration data on a byte-by-byte basis, and
  notes miscomparisons.
• If no Virtexs miscompare, then Configuration
  Scrubber returns to idle state.
• If a Virtex miscompares, its configuration memory
  is cleared and reloaded from the PROM. At the
  next system sync, it will be resynchronized with
  the other two. No loss of system function.
• If more than one Virtex miscompares with the
  others, all erroneous units are cleared and
  reloaded from the PROM (just as is done on
  power-up). AFPGA holds all state information so
  XFPGAs can pick up where they left off when the
  next resynchronization occurs. Command and
  telemetry are lost until resynchronization.

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TM Status

• Existing flight TM built in 2003 for SLIC per
  GE2055700
• Mods for SpaceCube interface code (Xilinx) was
  completed and tested on EDU
• New Actel FPGA (UMC die) was programmed and
  installed in the flight unit

choke
XO
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RNS SpaceCube Packaging Design

• Mechanical dimension 5.58W x 7.03L x 4.60H
  (inch)
• RNS SpaceCube contains Seven Circuit Cards.
• Five slice housing and cover machined from
  Aluminum alloy 6061-T651
• Min. Side Wall thickness
• 80 mils (bottom housing)
• 52 mils (connector panel)
• 100 mils (side walls base plate)
• Calculated weight 8.50 LBS
• Maximum torque for mating connector hardware 3
  IN/LBS
• Mounting and assembly 14 x 8-32 fasteners
• Finish Chemical conversion coating, color Gold,
  per Mil-C-5541, Class 3..
• Tapped holes are blind or exit external to box
  for debris control
• Mating surface flatness lt .010 with 125 micro
  inch rms finish

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Space Cube IRAD Baseline Capabilities
SpaceCube Architecture

• SERIAL INTERFACES
• 32 x LVDS serial pairs
• Support Ethernet, SpaceWire, or custom interface.
  
• 16550 compatible UARTs
• Aeroflex LVDS drivers and Receivers
• RS422 can be substituted for LVDS if desired
• STACKING CONNECTOR INTERFACE
• Airborne Connector
• 72 pins
• Design uses no backplane or motherboard.
• Low speed internal bus 400Kbps Redundant I2C
• High speed bus TBD Redundant
• Power Pins 3.3V, 5V
• RAD-HARD SCRUBBER
• UT6325 RadHard Eclipse FPGA
• 320,000 usable system gates
• 24 dual-port RadHard SRAM modules
• RadHard to 300K rad(Si)/sec
• OTHER PERIPHERAL INTERFACES

• ELECTRICAL SPECIFICATION
• 21V to 35V voltage input through optional low
  voltage power converter card slice
• Power Slice can provide
• 5V_at_ 2 Amps
• 3.3V_at_ 6 Amps
• 2.5V_at_ 4 Amps
• all voltages are tolerant to 10 / -10
• SAFETY
• SDRAM power is switched separately to handle any
  potential latchup conditions.
• ENVIRONMENTAL SPECIFICATION
• -20C to 55C (operating Baseplate temperature)
• -40C to 85C (storage baseplate temperature)
• 10 to 90 Relative Humidity, non-condensing
  (storage)
• MECHANICAL SPECIFICATION
• 4 inches x 4 inches (PCB)
• Box slice 4.25 inches x 4.25 inches x .75
  inches/slice
• single board, double sided
• I/O connectors
• 72 pin, Airborne Stacking

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SpaceCube IRAD Processor Slice
SpaceCube Architecture

• SpaceCube processor slice is a miniaturized CDH
  system on a single 4 x 4 inch board
• Processing power is provided by 4 PowerPC 405
  processors which can be run either in parallel
  for speed or in a quad redundant voting scheme
  for SEU immunity
• Each PowerPC has its own independent SDRAM for
  program code/OS use.
• A soft-core SpaceRISC microcontroller is
  instantiated in the radiation hardened Aeroflex
  FPGA and acts as the monitor and controller for
  the PowerPCs and the Virtex logic.
• SpaceRISC is instruction set compatible with the
  PIC16F86 Microcontroller
• SpaceRISC is responsible for loading/re-loading
  the PowerPC code and scrubbing the Virtex
  configuration memory.
• SpaceRISC is also the I2C controller

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SpaceCube IRAD Processor Slice
SpaceCube Architecture

• SpaceCube Processor Slice provides configurable
  LVDS (or RS-422) I/O which can be used with IP
  Cores to implement a variety of interfaces such
  as SpaceWire, Ethernet, USB and CameraLink.
• Cores are available to perform most encoding
  functions Reed-Solomon, Convolutional, AES
  Decryption.

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Radiation Mitigation Redundancy
SpaceCube Architecture

• SpaceCube Processor Slice utilizes Xilinx Virtex
  devices to perform many of its core functions.
• These devices have a very high total dose
  tolerance, but are susceptible to SEUs.
• To eliminate the SEU effects, QMR (Quad Module
  Redundancy) is used.
• In a QMR scheme, the design is instantiated four
  times, twice in each Xilinx. These are voted
  together and if one output is different, it is
  discarded.
• User logic is scrubbed to prevent SEUs from
  corrupting instantiated designs.
• Processors are hard cores within the devices.
• SEU performance of processor cores Tested by GSFC
  in September 05.

• Each Virtex device is split into two functional
  units consisting of a processor and its
  peripherals
• Device level floor planning is used to ensure
  that two instantiations are physically separate
  to reduce the effects of multi-bit SEUs.

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Radiation Mitigation (Voting)
SpaceCube Architecture

• Two types of voting are implemented in SpaceCube
• Packet Based Voting is used for low volume, high
  reliability data generated by the PowerPCs. This
  data is sent to the SpaceRISC via serial port and
  voted on byte by byte by the SpaceRISC.
• Stream Based Voting is used for high volume data
  such as Ethernet or SpaceWire. Stream data is
  buffered using FIFOs within the Virtex, then sent
  to hard voters in the Aeroflex and voted bit by
  bit.
• Synchronization is handled by the Aeroflex.
• Errors detected and corrected by either voting
  scheme are reported to the SpaceRISC for
  inclusion in telemetry.

• For each output channel (e.g. MSM1, MSM2, Ku-band
  downlink, etc.) there are
• Four Parallel-Input-Serial-Output FIFOs (one per
  Xilinx PowerPC, located in Xilinx)
• One Control Line from Aeroflex to Xilinx(s) to
  initiate FIFO serial output
• One 4-input voter in Aeroflex
• SCuP board has four synchronous serial lines from
  Xilinx to Aeroflex (one per PowerPC)
• SCuP board has one synchronous serial line from
  Aeroflex to all four Xilinx PowerPCs.

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POWER 2 Slice
CCA, LVPC 2
Processor 2 Slice
VIM Slice
Processor 1 Slice
POWER 1 Slice
CCA, DCC 2
CCA, Processor 2
CCA, VIM
CCA, Processor 1
CCA, DCC 1
Front Cover
CCA, LVPC 1
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SpaceCube Software Loads for RNWS