System pre

1
System pre commissioning / preliminary
ideas Alice TPC FEE Meeting CERN 1314 Jan
2005 Roberto Campagnolo
2
ALICE TPC FEE Status and short-term planning

• The mass production of the FECs is well advanced
  and it will be completed by March (300 FEC/w)
• The mass Test of the FECs is going on and it
  should be completed by April (80 FEC/d)
• The design phase of the backplanes is completed,
  some produced and tested with good results
• The final prototype of the RCU is going to be
  available by the end of January
• The DCS boards are currently under production
• The SIU with rad-tolerant FPGA (ACTEL) is in
  design phase
• (The mass production of the Backplanes will start
  after the complete validation of the RCU
  prototype)
• It is then envisaged to have a complete TPC
  readout sector available at Cern.
• This set up should be available a.s.a.p.
  (March) and it will be useful to exercise the
  FEE and other
• components before to start the TPC FEE
  commissioning phase (foreseen by June 2005)

3
The RCU project phases and deadline

•  
• Completion of the firmware implemented in the
  FPGA of the RCU (well advanced).
• Finalization of the hardware design and
  fabrication of a prototype (well advanced).
• 4 cards are going to be built 2 Cern 1 Bergen
  1 GSI (for mechanics)
• Validation of the prototype test and
  characterization of a complete readout partition
  consisting of 25 FECs, the readout and control
  backplane, the RCU, DAQ (DDLRORC), DCS and TTC
  system. Verification of the correct alignments
  between 2 (or more) systems .
• 
  
  
• Production of 250 boards provisioning of the
  components/ cost estimation / selection of an
  house / market survey / tendering
• PCB production and assembly (preferably made by
  the same firm in charge of the PCB production).
• Mass test
• 
  
• The full cycle must be completed by June
  2005

4
Single RCU set-up
Power supplies-laboratory type 4.3V, 25A and 3.3
V 50A
Power distribution rail
ISE 6.3i ChipScope
XlxPC4
Backplane
RCU
jtag
DAQ
DCS board
Backplane
QTZ on-board
Ethernet Boot option
Ethernet
DDL SIU
FPGA
L1 (Funct. Gen.)
40MHz
(option) VGAmonitorKeyboardMouse
Serial terminal (Falco)
busy signal
5
Notes about the Local Trigger Crate and DAQ

• We assembled a VME trigger crate based on a CCT
  VP110 processor,
• such processor is probably, but not yet decided,
  the one to use for the ALICE exp.
• ( radiation tests to be done)
• The boot is actually done via the Hard Disk ( the
  network option will be preferable for a
• Central software maintenance).
• The low-level operations are controlled by an
  ASCII terminal ( Falco)
• The connection to Ethernet allows a graphical
  user interface (i.e. using Exceed on a pc)
• As a option, it is possible to buy a VGA
  Keyboard/mouse interface (650CHF).
• The Local Trigger Unit allows the generation of
  legal and illegal trigger sequence,
• to work with the busy signal and to dispose of
  the L1 trigger.
• The interface to the DAQ has to be done via the
  Experiment Control System.
• 
  ? the latest version of DATE (v 5.0) is
  required.
• The DDL hardware actually in use in the RCU lab.
  is based on the pRORC with
• the Altera-based SIU .

6
Validation of the RCU prototype
Aim To verify that the prototype fulfills
all the design requirements before to launch

the mass production. The main verification and
functional tests are the following 1 -Supply
voltages and currents 2 -Test of RCU-FPGA
Readout interface (Accessibility test of
all CSRs, Control and Readout paths. Combination
of FEC and Altro tests) 3 -Communication with
DCS, TTC system and DAQ 4 -Initialization of
the FECs 5 -Generation of the Trigger and Clock
signals 6 -Exercising the Readout of FEC with
different patterns stored in the ALTROs
Pedestals memory 7 -Generation of Legal and
Illegal trigger sequences 8 -Verification of
the logic for busy / trigger accept / reject 9
-Readout of Trigger related data at various speed
10 -Test of RCU-FPGA Control Network interface
(BC accessibility tests via the I2C) 11 -Error
and Interrupt signals handling 12 -DCS
operations ? ( Communication , Error Handling
) 13 Scrubbing and Re-Configuration feature ()
7
Test Software

• Set of programs required for the validation
  phase
•  
• To test the register accessibility 
• To help in finding misbehaviors in writing and
  reading back
• To Configure the System
• To write in the pedestal and readout memories
  different patterns
• To Check the Readout of trigger related data
• To verify the slow control Functionalities
• To handle Error and Interrupt conditions
• To verify the Sparse readout and Test-Mode
  readout
• On line monitor / Data quality monitor checker
•  
•   
• The certification Database can be the same
  already used for other mass-test setups (FEC or
  ALTRO). The RCU cards will be identified by a bar
  code and the DB interfaced to the reader.

8
Software available for test purposes
LabView platform
/home/rcu/rcu/Linux/Tests/LabviewConfig/
../Monitor/
../Configuration/
../Analysis/
Send_ALTROCommand.vi
Monitor.vi
Analysis.vi
Full_Analysis.vi (with full decoding)
Write_ALTRORegister.vi
VIs
VIs
Read_ALTRORegister.vi
Send_AFL_ACL.vi
LaunchTestmode.vi
ManualConfiguration.vi
VIs

• ? They represents a basic set. We still need to
  improve/develop some functionalities
• (i.e. the way to configure the ALTROs, the
  Error Debugging, the Slow Control operations )
• DCS communication , FPGA re-Configuration
• ? Is Labview fast and reliable enough for the
  mass tests, as well ? I think so.

9
Alignment verification
Power supplies-laboratory type 4.3V, 25A and 3.3
V 50A
Power distribution rail
Front End Cards with input stage modified ( PASA
by-passed)
25
25
FEC
FEC
We verify the correct alignment between the 2
systems for different trigger rate and clock
phases
Backplane
Backplane
RCU
RCU
QTZ
QTZ
DCS board
DCS board
Backplane
Backplane
1
1
FEC
FEC
DDL SIU
DDL SIU
FPGA
FPGA
splitter
Rclk , L1(synch)
Busy
Delay unit
(Analysis software missed)
10
Sector test

• What is the purpose of this set up ?
• Exercising the FEE of a full sector,
• tuning of DCS parameters,
• verification of mechanical aspects,
• cooling and LV distribution,
• concurrent readout of 6 RCUs,
• trigger alignment,
• .
• When it could be available ?
• In March
• Where to install it ?
• Either room 13 R-025 (RCU lab.)
• or, better, hall 167 (experimental area,
• to be discussed with Joachim)
• What do we need ?
• ( next slide )

C6 20 FECs
C5 20 FECs
Outer chamber
FEC
C4 20 FECs
C3 18 FECs
C2 25 FECs
Inner chamber
C1 18 FECs
11
What do we need ?

•  
• DCS
• 2(6) new DCS boards
•  
• DAQ
• 1 (2) Local Data Concentrator PC
• 2 (6) DRORC
• 2 (6) DDL kit (with fibers)
• (1 Global Data Concentrator)
•  
• Software
• Last release of DATE (5.0?)
• LTU trigger software
• ECS
• On-line Monitor/ Data quality monitor-checker

• Mechanics and Detector parts
• Service support wheel SECTOR
• Specific jig to keep the whole mechanics
• An Inner and a Readout Chamber
•  
• Electromechanics
• 40 m power bars
• Power rails to supply the 121 FECs
• FECs' power supply cables
• Grounding bridges (between FECs and SSW)
•  
• Cooling
• Cooling plates for 121 FECs
• (when available 6 c.p. for RCU)
• Cooling system
• FECs and RCUs
• 29 (121) FECs
• 2 (6) RCUs

12
End of presentation
13
The RCU laboratory _at_ CERN (13 R-021,025)
(height 2.3 - 2.6 m)
14
Validation of the backplanes

• On top of the readout tests, where the access to
  registers and readout of defined patterns are
  exercised, it is fundamental to verify the signal
  integrity and the noise margin for complete
  loaded pcb-backplanes.
• Considering the GTL threshold set around 950mV,
  the test must verify the margins for the
  following combinations
• The 2 branches x 6 types of backplane
• Different load conditions (all cards connected
  but with different number of cards ON or OFF)
• Distribution of the clock signals (readout clock
  and jittering in the Sampling clock)

1(of the 2) branch of the backplane
Example of GTL signal integrity measurement
FEC slot
GTLbus termination
RCU slot
15
The RCU commissioning project
16
TPC FEE elements
Overall TPC 4356 Front End Card
216 Readout Control Unit
36 x (12 different PCB backplanes )
Front End Cards
25
FEC 128 ch
Rdo Backplane
COUNTING ROOM
Readout Control Unit
FEC 128 ch
14
FEC 128 ch
13
Detector Data Link
SIU (DDL-SIU)
(RORC)
(ALTRO Bus and Slow-control Interfaces)
DETECTOR
DCS
Ethernet
12
(DCS)
FEC 128 ch
DCS int. (Ethernet)
RCU
Trigger int. (TTC-RX)
TTC optical Link (Clock, L1 and L2 )
(TTC)
FEC 128 ch
2
FEC 128 ch
1
2 branches of PCB Readout Backplanes