Designing Pipelined ADC's using Global Optimization

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Designing Pipelined ADC'susing Global
Optimization

• Johan Vanderhaegen
• Bob Brodersen
• BWRC Retreat Winter 2004

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Outline

• Pipelined ADC
• Global optimization
• Optimization example SC OTA
• Optimization example Pipelined ADC
• Layout Generation

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Pipelined ADC

• Quantize signal and calculate residue
• Accuracy bottleneck residue amplifier gain
  accuracy
• Speed bottleneck residue amplifier settling
• Design parameter B

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ADC Design Constraints
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Outline

• Pipelined ADC
• Global optimization
• Optimization example SC OTA
• Optimization example Pipelined ADC
• Layout Generation

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Analog Design Automation Approaches

• Knowledge-based Analog Sizing (1980-)
• Procedural design plan
• Heuristic design knowledge hard to capture
• Optimization-based Analog Sizing (1990-)
• Equation based optimization
• Manually derived
• Symbolic analysis
• Simulation based optimization
• Circuits at cell design level
• Behavioral models at higher levels

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Global Optimization

• Global optimization problem in standard form
• minimize f0(x)
• subject to fi(x) 0 i 1,,m
• hk(x) 0 k 1,,p
• Mapping of analog design constraintsas
  optimization problem
• Minimize power and/or area
• Constraints on performance metrics
• Computationally hard problem

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Global Optimization

• Reversed Geometric Programming
• minimize g0(x)
• subject to gi(x) 0 i 1,,m
• gj(x) 0 j 1,,n
• Computationally hard problem ?
• But
• we separated the hard and the easy
  constraints
• there are relatively few reversed constraints

convex
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MOSFET Model (Saturation)
10 error over 3 decades of current
ST 0.13 mm technology
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Outline

• Pipelined ADC
• Global optimization
• Optimization example SC OTA
• Optimization example Pipelined ADC
• Layout Generation

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Optimization Example SC OTA
Vpp 1V SNR 74 dB varying fs ST 0.18 µm
technology
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Optimization Example SC OTA
simulation /- 5
ST 0.18 µm technology
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Outline

• Pipelined ADC
• Global optimization
• Optimization example SC OTA
• Optimization example Pipelined ADC
• Layout Generation

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Optimization Pipelined ADC

• Quantize signal and calculate residue
• Accuracy bottleneck residue amplifier gain
  accuracy
• Speed bottleneck residue amplifier settling
• Design parameter B

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Pipelined ADC - OTA

• High speed
• Low gain
• Nonlinear

Vpp 1V SNR 65 dB varying fs ST 0.13 µm
technology
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Pipelined ADC - OTA
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Pipelined ADC
Power efficient designs
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Outline

• Pipelined ADC
• Global optimization
• Optimization example SC OTA
• Optimization example Pipelined ADC
• Layout Generation

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Layout Generation
Layout Generation Program
Optimized Schematic
Layout
Device Generation
Component Placement
Routing
NeoCell Module Generators
Cadence Router
Schematic Based Placement
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Device Generation
Name
Schematic
Layout
Cascode MOSFET
Differential-Pair (Quad-FET)
Differential-Pair (Quad-FET)
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Component Placement
Hierarchical Schematic
Hierarchical Layout
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Outline

• Pipelined ADC
• Global optimization
• Optimization example SC OTA
• Optimization example Pipelined ADC
• Layout Generation