Analysis of QuasiStatic Scheduling Techniques in a Virtualized Reconfigurable Machine

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Analysis of QuasiStaticScheduling Techniques in
aVirtualized Reconfigurable Machine

• Yury Markovskiy, Eylon Caspi, Randy Huang,
• Joseph Yeh, Michael Chu, John Wawrzynek
• UC Berkeley
• BRASS Group
• André DeHon
• California Institute of Technology

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Outline

• Hardware Virtualization
• SCORE model
• Run-time scheduler
• Fully Dynamic
• Quasi-Static
• Results
• 7x reduction in scheduling overhead
• App performance improved by a factor of 2-7.
• Conclusion

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Hardware Virtualization

• Traditional Mapping Tools
• Expose resource constraints to designer

• HW virtualization enables
• App compatibility/longevity across a device
  family
• Automatic performance scaling on larger devices

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Stream Computation Organized for Reconfigurable
Execution (SCORE) (1)

• Data-flow based framework
• Programming Model
• Execution Environment
• Hardware Platform

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Stream Computation Organized for Reconfigurable
Execution (SCORE) (2)

• Array Reconfiguration

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Run-time Scheduler

• Run-time scheduling (late binding of resources)
• Benefit automatic performance scaling
• Extra burden scheduler
• Complex optimization with multiple simultaneous
  constraints(CPs, CMBs, and network) ? NP-hard
  problem

• Space of scheduling solutions
• Range in quality and complexity
• Tradeoffs timeslice vs asynchronous or dynamic
  vs static

• What is the right timeslice size?
• Depends on an applications run-time behavior
• Affected by the scheduler overhead (lower bound)

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Problem Statement

• SCORE Micro-architecture
• Parallel reconfiguration of independent CPs/CMBs
• Reconfiguration time is thousands of cycles
• Problem
• Investigate scheduling cost
• Reduce it to a minimum (comparable to
  reconfiguration time)
• Understand its effect on application run-times.

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Initial Scheduling Solution

• Fully Dynamic Scheduler
• Perform scheduling operation each timeslice

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Fully Dynamic Scheduler (1)

• Two types of overhead
• Scheduler (avg. 124 Kcycles)
• Reconfiguration array global controller (avg.
  3.5 Kcycles)
• Average overhead per timeslice gt 127 Kcycles

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Fully Dynamic Scheduler (2)

• Total Execution Time
• Scheduler Overhead is on average 36 of execution
  time
• Timeslice Size 250Kcycles.

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Quasi-Static Scheduler

• Timeslice size
• Dynamically controlled by array hardware stall
  detect.
• Hardware continuously (or at small intervals)
  monitors array activity.

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Results (1)

• A low overhead scheduling solution
• Scheduler overhead (avg. 14Kcycles)
• Reconfiguration (avg. 4Kcycles)

• 7x average reduction in overhead

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Results (2)

• 4.5x average application speedup
• Reduction in overhead AND
• Improvement in scheduling quality

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Results Summary

• Tested applications
• Image de/compression consist of both dynamic
  and static rate operators.
• All demonstrate similar speedups under
  Quasi-Static scheduler.
• Performance improvements can be attributed to
• Reduced scheduler overhead
• Improved scheduling quality
• Global rather than local (BFS) view as in dynamic
  scheduler
• Reduction of the lower bound of timeslice size
• Expands the space of apps well suited for
  execution under a virtualized hardware
• Retained powerful semantics of dynamic
  data-dependent dataflow

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Conclusion

• Run-time scheduler
• Required for automatic scaling under hardware
  virtualization
• Run-time overhead sets lower bound on the size of
  scheduling step (response time)
• Restricting applicability of virtualized hardware
• Makes this model impractical for some apps
• Low overhead run-time scheduling is achievable
• Without semantic restrictions
• With higher (or comparable) scheduling quality.
• 7x reduction in overhead and simultaneous
• Performance improvement of 2-7x.
• OS is a viable alternative to manual scheduling.

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Thank You

• Thanks to
• DARPA, Xilinx and STMicro
• For more information
• http//brass.cs.berkeley.edu/SCORE