Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANS)

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Project IEEE P802.15 Working Group for Wireless
Personal Area Networks (WPANS)
doc. IEEE 802. 15-04-0467-00-003a
September 2004

• Submission Title Implementation of High Speed
  FFT processor for MB-OFDM System
• Date Submitted September 2004
• Revised
• Source Sang-sung Choi, Sang-in Cho
• Company Electronics and Telecommunications
  Research Institute
• Address 161 Gajeong-dong, Yuseong-gu, Daejeon,
  305-350 Korea
• Voice 82-42-860-6722, FAX
  82-42-860-5199, E-mail sschoi_at_etri.re.kr
• Re Technical contribution
• Abstract This presentation presents the
  implementation method of IFFT/FFT processor for
  MB-OFDM UWB system
• Purpose Technical contribution to implement
  IFFT/FFT processor proposed for MB-OFDM UWB
  system
• Notice This document has been prepared to assist
  the IEEE P802.15. It is offered as a basis for
  discussion and is not binding on the contributing
  individual or organization. The material in this
  document is subject to change in form and content
  after further study. The contributor reserves the
  right to add, amend or withdraw material
  contained herein.
• Release The contributor acknowledges and accepts
  that this contribution becomes the property of
  IEEE and may be made publicly available by
  P802.15.

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Implementation of High Speed FFT processor for
MB-OFDM System

• Sang-Sung Choi (sschoi_at_etri.re.kr)
• Sang-In Cho (sicho_at_etri.re.kr)

www.etri.re.kr
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Introduction

• MB-OFDM UWB proposal requires high speed
  IFFT/FFT processors with 128-point computation.
• Digital signals processed in IFFT processor
  change into analog signals by DAC, and then pass
  through the sharp LPF to satisfy the transmitting
  PSD mask.
• - Transmitter using 128-point IFFT processor
  (DAC speed 528MHz)
• - LPF shape Frequency spectrum of OFDM
  signal after DAC

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Introduction

• The TX LPF is very important to determine the
  transmit PSD mask
• of MB-OFDM UWB system, but the TX LPF design
  is not easy to
• satisfy the Transmit PSD mask of MB-OFDM.
• Two methods are considered to design the TX LPF
  satisfying the
• transmit PSD mask.
• 1) fix 528MHz sampling rate of DAC , and
  design high order TX LPF
• 2) increase sampling rate of DAC, and reduce
  the order of TX LPF
• Use 2 times over-sample rate at DAC to design
  the TX LPF.
• - Reduce the order of TX LPF
• - It has advantage of the performance
  compared to method 1).
• ? Presented by DOC IEEE802.15-03/275r0
• There are trade-offs between two methods for
  considering power
• consumption and gate size etc.
• ? ETRI is developing a prototype UWB system
  using 256-point IFFT
• processor (DAC speed 1056MHz)

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Proposed IFFT Processor Approach

• For easy low pass filtering of 528MHz baseband
  signal after DAC, we have to make space between
  OFDM signals that are repeated in frequency
  spectrum, which is accomplished by 128-point
  zero-padding.
• - Transmitter using 256-point IFFT processor
  (DAC speed 1056MHz)
• - LPF shape Frequency spectrum of OFDM
  signal after DAC

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IFFT/FFT Processor Specification

• Input data of FFT processor are QPSK modulated
  128-point complex data
• Input data of IFFT processor become 256-point
  that consisted of QPSK modulated 128-point
  complex data and 128-point zeros.
• - Input data of original IFFT processor
  (128-point QPSK data)
• - Input data of proposed IFFT processor
  (128-point QPSK data 128-point zeros)

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Proposed transceiver for MB-OFDM UWB PHY proposal
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Characteristics of Multipliers

• Multiplier is one of the most dominant elements
• in FFT/IFFT implementation
• Standard 2s Complement Multiplier
• (W-bit) x (W-bit) (2W-1)-bit
• Many DSP applications need only W-bit products
• Fixed-Width Multiplier
• Quantization to W-bit by eliminating (W-1) Least
  Significant Bits
• Can reduce area by approximately 50 but
  Truncation Error is introduced
• Proper Error Compensation Bias needed
• Canonic Signed Digit Multiplier
• Constant coefficient
• 33 fewer nonzero digits than 2s complement
  numbers
• Modified Booth Multiplier
• Variable coefficient
• The number of partial products has been reduced
  to W/2
• These multipliers can achieve about 40 reduction
  in area and power consumption

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The radix-24 structure of FFT processor
DFT
Radix-2 structure
Radix-24 structure
CSD multiplier
CSD multiplier
Modified Booth multiplier
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The structure of 256-point IFFT processor

• 32-point Radix-24 FFT structure
• 8-level parallelism
• DIF (Decimation In Frequency), SDF (Single Delay
  Feedback)
• Fixed CSD Modified Booth multipliers used

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The structure of 256-point IFFT processor

• Butterfly unit 48
• -j multiplier 22
• CSD multiplier 16
• Modified Booth Multiplier 8

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The structure of 256-point IFFT processor
CSD multiplier
CSD multiplier
Modified Booth multiplier
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The structure of 128-point FFT processor

• 32-point Radix-24 FFT structure
• 4-level parallelism
• DIF (Decimation In Frequency), SDF (Single Delay
  Feedback)
• Fixed CSD Modified Booth multipliers used

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The structure of 128-point FFT processor
CSD multiplier
CSD multiplier
Modified Booth multiplier

• Butterfly unit 24
• -j multiplier 11
• CSD multiplier 8
• Modified Booth Multiplier 4

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Simulation result of 256-point IFFT processor
Constellation

• Input Bit resolution 3
• Output bit resolution 20
• Multiplier coefficient bit 10
• SQNR 52dB

• Input Bit resolution 3
• Output bit resolution 11
• Multiplier coefficient bit 8
• SQNR 30dB

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Simulation result of 128-point FFT processor
Constellation

• Input Bit resolution 10
• Output bit resolution 20
• Multiplier coefficient bit 10
• SQNR 52dB

• Input Bit resolution 10
• Output bit resolution 12
• Multiplier coefficient bit 8
• SQNR 30dB

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Summary of simulations

• IFFT processor

Points Parallel level SQNR (dB) Gate Count
256 8 52 about 100k
256 8 30 about 80k

• FFT processor

Points Parallel level SQNR (dB) Gate Count
128 4 52 about 50k
128 4 30 about 40k
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Conclusion

• 256-point IFFT processing for easy Low Pass
  Filtering
• Parallel structure for high speed signal
  processing
• IFFT/FFT processor
• 32-point radix-24 DIF SDF structure
• Small area, low power, high speed operation
• Canonic Signed Digit Multiplier constant
  coefficients
• Modified Booth Multiplier variable coefficients

IFFT processor FFT processor
Point 256-point 128-point
Parallelism 8 4
Number of input data (sample/clock) 4 4
Throughput (sample/clock) 8 4
Latency (except S/P, reverse unit) 32 32
Number of gates (30dB SQNR) About 80K About 40K