Architecture For Variable Length Combined FFT, DCT and MWT Transform Hardware for a Multimode Wirele

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• Architecture For Variable Length Combined FFT,
  DCT and MWT Transform Hardware for a Multimode
  Wireless System

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High Performance Cognitive Radio Platform with
Integrated Physical and Network Layer
Capabilities
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Introduction

• Combined Wireless base band processor
  architecture targeting
• FFT for Orthogonal Frequency Division
  Multiplexing (OFDM).
• Discrete Cosine Transform (DCT) for video and
  audio compression.
• Modified Walsh Transform (MWT) for demodulation
  of the Complementary Code Key (CCK).
• The Architecture is a Variable-length and is
  suitable for multimode and multi standard OFDM
  communication system, digital audio broadcasting
  (DAB), digital video broadcasting terrestrial
  (DVB-T), very high speed digital subscriber loop
  (VDSL), and asymmetric digital subscriber loop
  (ADSL).
• It also does Joint Photographic Expert Group
  (JPEG) and Moving Picture Expert Group (MPEG).

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Why combined architecture?

• Useful for both base band processing and
  multimedia application acceleration.
• DAB (Digital Audio Broadcasting) DVB (Digital
  Video Broadcasting) or a 4th generation wireless
  multimedia terminal.
• Saves AREA and POWER !!!()
• Feature size of nano,
• Leakage power a Hardware
• Therefore, Combined multiple hardware blocks gt
  reduced hardware and power !

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Why Variable length?

• FFT and IFFT used for Modulation/Demodulation in
  several OFDM standards.
• Various FFT sizes are required to make the
  processor scalable!
• Building blocks that can be configured for
  computing different algorithms.
• VARIABLE LENGTH is a necessity in multimode
  wireless system.

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Research Till Date
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Proposed Architecture

• Combined, reconfigurable hardware for computation
  of
• FFT for different OFDM standards.
• DCT for multimedia applications.
• MWT for 802.11b standard.
• At different times using a novel variable length
  architecture .
• Pipelined FFT is preferred over memory based FFT
  architecture for higher throughput at the cost of
  increased hardware.
• Pipelined FFT is the best choice to implement a
  high speed, large N FFT due to its regular
  structure and simple control.

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Why R22SDF?

• R2MDC
• 50 utilization of butterflies and multipliers.
• log2N-2 multipliers , log2N radix-2 butterflies
  and 3/2 N-2 registers.
• R4MDC
• log4N multipliers , log4N full radix-4
  butterflies , 5/2 N-4 registers.
• R2SDF
• Same number of butterflies and multipliers as
  R2MDC but uses N-1 registers, minimal memory!!
• R4SDF
• Multiplier utilization increased to 75 but
  butterfly utilization drops to 25.
• log4N-1 multipliers, log4N full radix-4
  butterflies ,storage of size N-1.
• R22SDF
• Radix-4 multiplicative complexity but radix-2
  butterfly structure.
• log4N-1 multipliers and N-1 registers.

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How to implement DCT using FFT?

• DFT of a finite duration sequence x(k) of length
  N.
• DCT is the real part of the DFT of the sequence
  ß(k) multiplied by k/2 a(k) and a twiddle factor
  of W2N.

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How to implement MWT using FFT?

• MWT for 0 l 64 , where l is the number of
  output samples.
• The transform expands 8 input samples into 64
  output samples.
• We modify the FFT machinery to compute MWT
• Short circuit the multiplication with the twiddle
  factor .
• Set variable length to 64 and assign
• x(0) a, x(1) b,x(4)c,x(5)d,
• x(16) e,x(17)f,x(20)g,x(21)h
• All other entries are zeroed.

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Combined FFT,DCT MWT
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FFT Processor
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FFT Processor

• To compute N FFT points, log4N radix -22 stages
  are used.
• For length N that cannot be expressed as power of
  4, radix-2 and radix -22 stages are used.
• Radix-2 and radix- 22 are never used
  simultaneously, so stages 7 ,3 and 1 can be
  reconfigured between radix 22 and radix-2
  processing as needed.
• All internal control is managed by a control
  counter for synchronizing the stages.
• After a latency of N-1 clock cycles, processor
  produces one output for each input value.

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Radix-22
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Butterfly
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(No Transcript)
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Radix - 22

• The complex multiplier of radix-4 is replaced
  with a trivial multiplier that only multiplies by
  j i.e. the real and the imaginary parts swap
  places and the new imaginary part changes sign.
• The control is now simple and the memory
  requirement is the smallest possible for a
  pipelined FFT processor.

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DCT Processor
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DCT Processor

• Input reordering is done using the DCT Reorder
  Unit.
• To calculate 2-D DCT, bypass the input directly
  to DCT Reorder Unit.
• The reordered input is passed to stages 4 and 3
  to obtain the intermediate value of 1-D DCT.
• This value is then multiplied by values stored in
  the DCT ROM.
• The k DCT ROM prestores the product of
• W2N and a(k).

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DCT Processor

• Real value of that product is stored in the
  Transpose Buffer and the output of the Transpose
  Buffer is passed to the second DCT Reorder unit.
• The reordered output is passed to stages 2 and 1.
• Intermediate value k obtained after passing
  through these stages is multiplied by the
  product of W2N and a(k) prestored in the
  second DCT ROM.
• The real value of this product is the 2-D DCT of
  the input values.
• The control unit generates the addresses for the
  appropriate values corresponding to a particular
  N.

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DCT Processor

• The two RAMs accept data written into them in
  row-major order and retrieve data during read-out
  in column-major order, thus, transposing the
  data.
• The memory sub-system only generates one output
  word at a time, so both RAM1 and RAM2 cannot be
  read out simultaneously.
• Also, the WE control forces both the RAMs to be
  in opposite READ/WRITE states at any given time.

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MWT Processor
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MWT Processor

• Length N 64 and so the stages 7, 6, 5 and 4
  are turned off and bypass the input to stages 3,
  2 and 1.
• We modify the FFT machinery to compute MWT
• Short circuit the multiplication with the twiddle
  factor.
• Set variable length to 64 and assign
• x(0) a, x(1) b,x(4)c,x(5)d,
• x(16) e,x(17)f,x(20)g,x(21)h
• All other entries are zeroed.

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Standards to be met

• OFDM and MWT The requirements of different OFDM
  standards and the corresponding clock rates can
  be tabulated as

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Standards to be met

• JPEG and MPEG-4

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Work Plan
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Schedule
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Conclusion

• Thus we have proposed a novel combined wireless
  base band processor architecture.
• Radix 2 and Radix 22 is used in the
  implementation of FFT, DCT and MWT processor.
• By doing so we use fewer multipliers and gates,
  thus saving area and power.