Reconfigurable architectures for wireless communication systems

1
Reconfigurable architectures for wireless
communication systems

• Dottorato in Ingegneria elettronica e delle
  comunicazioni
• XVIII ciclo

Candidato Mario Nicola
Tutore prof. Maurizio Zamboni
2
Introduction

• Growth of wireless communications
• New emerging standards
• New applications
• High performance required
• Low time-to-market
• Low overall costs
• Flexibility is a key factor for modern wireless
  communication system

3
Approaches

• DSP (Digital Signal Processors)
• ASIP (Application Specific Instruction set
  Processors)
• Mixed approaches (e.g. processor FPGA)
• FPGA (Field Programmable Gate Arrays)
• ASIC (Application Specific Integrated Circuits)

4
Flexibility vs. application

• Different applications pose different constraints
• Prototypes
• Base stations
• Mobile terminals

• no power/size constraints
• costs not critical

• relaxed power/size constraints
• costs critical

• tight power/size constraints
• costs critical

5
Exploration

• Prototypes
• FPGA
• Channel emulator for baseband transceiver
  simulation
• Terminals
• ASIP
• Modulation for OFDM communication system

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FPGA

• Flexible hardware

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Case study channel emulator

• Need for fast and repeatable simulations of
  baseband terminals
• Combination of wideband transmissions and
  powerful channel codes implies low BER and PER
  values ? long simulations
• Sophisticated channel models ? high simulation
  complexity

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802.11n

• 802.11n is a WLAN based on OFDM
• Data are modulated/demodulated over several
  carriers using IFFT/FFT
• 802.11n reaches high reliability in presence of
  frequency selective multipath fading
• Support of multiple antenna implementations
  (MIMO)

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Channel model implementation

• Multipath and Doppler effect time variant FIR
  (tap value vs. scenario)
• MIMO one filter for each pair of
  receiving/transmitting antennas
• multiple AWGN generators due to thermal noise
  independence for each receiving antenna
• AGC block to adjust output dynamic (front-end
  effect emulation)

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Platform

• RealView Versatile Platform Baseboard for
  ARM926EJ-S

Expansion module equipped with Xilinx FPGA and
ZBT RAM
Base board equipped with ARM processor and
expansion modules
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Channel main parameters

• Ntx number of transmitting antennas
• Nrx number of receiving antennas
• Ntap number of paths (taps of FIR filter)
• Fs sampling frequency
• Tup update time for tap values

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Channel model and complexity
? (1/Tup)
2NtxNrxFs mult (2NtxNrx 3)Fs add
2NtxNrxNtapFs add
3NtxNrxNtapFs mult ((41)NtxNrxNtap Ntx) Fs add
2NrxFs add
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Simplified model

• Reduce the number of multiplications
• New sampling scheme for delayed signals

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Architecture
Values for taps of time variant FIR filter are
calculated off-line and stored in ZBT-RAM (up to
2.39 simulation time in a standard indoor
scenario).
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AWGN generator

• Low complexity, preferably without multipliers
• Central limit theorem
• Uniform generator with CASR and LFSR
• Random interleaver to reduce autocorrelation

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Channel emulator IP
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Reconfigurability

• Off-line reconfigurability (need synthesis)
• number and position of taps
• number of transmitting antennas
• number of receiving antennas
• On-line reconfigurability (no synthesis)
• seeds and energy for noise generation
• mobile speed
• simulated scenario

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Synthesis results

• Channel emulator for a MIMO 2x3, with a variable
  number of taps (Xilinx Virtex2 8000-4)

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Simulation results
channel B
channel D

• Simulations for 802.11n compliant
  transmitter-receiver, 64 QAM with convolutional
  code (SW complete model vs. HW simplified model)

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Channel emulator - Conclusions

• A reduced complexity channel emulator suitable
  for 802.11n simulation has been shown
• A communication bandwidth up to 63 MHz can be
  supported in real time simulation
• FPGAs result a good solution because are able to
  obtain both high performance and reconfigurability

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Additional notes

• A complete baseband UMTS transmitter-channel-recei
  ver chain has been implemented using a commercial
  FPGA based board (Nallatech Ballynuey 2).
• A complete baseband OFDM transmitter-
  channel-receiver chain is currently under
  development using a similar board (Nallatech
  Bennuey).

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ASIP

• Reconfigurability through software

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LISATek Design Flow
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ASIP Case Study - I

• In OFDM communications, IFFT/FFT are used for
  modulation/demodulation of data samples into/from
  several carriers

S/P
P/S
FFT
Mapper
Demapper
IFFT
S/P
P/S
channel
output data
input data
add prefix
discard prefix
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ASIP Case Study - II

• Case study with parameters from a realistic FFT
  implementation for OFDM

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ASIP Solution

• Targets
• Match flexibility and speed requirements
• Reduced design time
• Radix-2 FFT
• 2 Approaches (Optimized Data Path, Optimized
  Control Path)

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Optimized Data Path

• Complex data support, delayed branch, result
  bypassing
• 6-stage pipeline
• Specialized instructions
• butterfly, butterfly_ls

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Optimized Control Path

• Complex data support, delayed branch, result
  bypassing
• 6-stage pipeline
• Automatic Index Update (AIU)
• Zero Overhead Loops (ZOL)

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Data type selection

• Complex data supported by data path
• e.g. complex multiplication
• Memories and register file
• Data path can elaborate real part of data only,
  or imaginary part only or both of them
• Programmable by user (optional flag)

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Automatic Index Update

• Memory address stored in register
• Automatic increment of address after memory
  access
• Optional flags
• and rev
• Increment set by user
• SET_INCREMENT

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Zero Overhead Loop - I

• Two general purpose registers
• Addresses (start, target)
• Indexes (current value, initial value)

RE
IM
target address
start address
current value
initial value
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Zero Overhead Loop - II

• SET_STARTADDR R10, _at__label5
• SET_TARGETADDR R10, _at__label1
• SET_INITVALUE R11, 2
• SET_ZOL R11, R10
• SET_STARTADDR R12, _at__label4
• SET_TARGETADDR R12, _at__label2
• SET_INITVALUE R13, 2
• SET_ZOL R13, R12
• SET_STARTADDR R14, _at__label3
• SET_TARGETADDR R14, _at__label2
• SET_INITVALUE R15, 4
• SET_ZOL R15, R14

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Results and Comparison
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ASIP - Conclusions

• An ASIP approach for implementation of a wireless
  application has been explored
• ASIP approach
• meets speed constraints
• maintains high flexibility
• implies reduced design time

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Additional notes

• Other FFT algorithms have been explored as case
  study in ASIP development
• Radix-4
• Cached FFT
• Quick Fourier Transform
• Fourier transform through Hartley transform

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Final notes
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Conclusions

• FPGA and ASIP approaches have been explored
• Both approaches proved to be suitable for
  wireless communication system implementations
• Use of FPGAs, due to high power consumption,
  limited to prototypes and base stations

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Bibliography

• M. Nicola, G. Masera, M. Zamboni, H. Hishebabi,
  D. Kammler, G. Ascheid, H. Meyr, FFT processor
  a case study in ASIP development, IST 2005.
• A. Dassatti, M. Nicola, G. Masera, A. Concil, A.
  Poloni, High Performance Channel Model Hardware
  Emulator for 802.11n, FPT 2005.

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Acknowledgments

• Author acknowledges
• prof. Guido Masera for his valuable help