Electronics status

1
Electronics status

• Optical Readout Interface (ORI)
• Global Tracking Unit (GTU)
• TRAP yield and next production lot

2
ORI radiation test in Oslo
No permanently damaged components. Equivalent
time in years in blue, - the device
fails. Recovery after power cycle or switching
off for up to 12 hours (VR and Laser Driver). The
configuration of the CPLD and EEPROM was not
damaged.
Laser DriverLinear Technology LTC5100 100
VCSEL DiodeULM PhotonicsULM850-02-LC-TOSA 20
EEPROM24LC01 30
LVDS TransceiverNational SemiconductorDS90LV048A
30
SerializerTexas InstrumentsTLK2501 250
CPLDLatticeLC4256V 15-50
Voltage RegulatorsNational SemicondutorLP3962-3.
3 and -2.5 60-110
F.Rettig
http//www.kip.uni-heidelberg.de/wiki/TRD/index.ph
p/ImageOslo_Results_-_ALICE_Integration.pdf
3
ORI optical power
The optical power is reproducible from board to
board and in time (see ORI7). No radiation
effects (the laser diode of ORI4 was irradiated
but shows excellent power. The laser driver chip
has very good protection, by wrong parameters
(range, current) the fault condition properly
detected and diode switched off.
F.Rettig
4
ORI eye diagram
Laser driver configuration parameters optimized
for best eye diagrams
F.Rettig
5
Optical link production status
Production status Transmitter - 2 boards
prototype version, suitable for testing of the
ROBs different from 3A/B - 11 boards usable on
the ROBs, 3 of them irradiated but OK - 7
boards will be manually soldered soon - The
final version sent to MSC for production,
components available, 60 boards will be produced
in the next 3-5 weeks - Radiation test
done. Production status Receiver (for use with
the ACEX board) - 8 boards ready and tested
together with the ACEX boards - 4 new receivers
will be ready soon. Needed for ROB and ORI tests
and until GTU board ready to receive data from
the detector.
6
GTU Status

• 10 FPGAs ES4 received from Xilinx
• ES1 FPGA replaced by ES4 FPGA on one TMU board
• Tests so far
• smoke test OK
• I2C interface to the SFP modules stable
• first successful optical serial data
  transmission with one SFP/MGT
• PCI interface for configuration and first
  readout in progress, the PC recognizes the PCI
  core correctly.
• The second TMU board sent to MSC, the FPGA will
  be replaced by ES4. So Felix and Jan can work in
  parallel.

F.Rettig, J. de Cuveland
7
TRAP yield and next production lot

• Results from the last corner and production run
• 25 wafers (12 corner 13 production), 14400
  TRAPs tested
• 6245 of the TRAPs are error free (43)
• 8143 (56.5) usable (when ignoring ADC, DMEM and
  laser ID errors)
• In this 8143 0.7 with DMEM, 19 with ADC and 3
  with laser ID errors
• In the group of ADC errors normally only about
  10 have real ADC problems after bonding, the
  rest is due to bad contacts. In the corner wafers
  some of the ADC errors are actually ADCs with
  conversion gain out of the normal range. But we
  can accept higher conversion gain (smaller ADC
  range)
• The yield varies between 45 and 69 in the
  different wafers
• Strong correlation between the position of the
  TRAP on the wafer and the test results, see the
  next slides. Such correlation is not normal and
  was not observed in the so called Patched 2
  wafers.
• The next production lot (50 wafers) started
  today.

8
TRAP patched 2 wafers
of good TRAPs
of good TRAPs
Column
Reticle position
number of good TRAPs
of good TRAPs
Line
http//www.kip.uni-heidelberg.de/wiki/TRD/index.ph
p/ImageWafer-yield_column_line_ret.ppt
9
TRAP prod. wafers Feb 2006
of good TRAPs
of good TRAPs
Column
Reticle position
number of good TRAPs
of good TRAPs
Line
http//www.kip.uni-heidelberg.de/wiki/TRD/index.ph
p/ImageWafer-yield_column_line_ret.ppt