Project Status

1
Project Status
Expect Tape-Out at End of Summer

• Status
• Analog Front-end Design Nearly Complete
• OSC, DLL, CLKGEN, ADC, CTRL, LNA -- done
• Gain Stages still examining ways to lower
  power
• TX still examining co-design aspects
• Layout on LNA done Due to start on rest of
  front-end
• Digital Back-end Design Complete and in
  Place/Route
• Still need more verification work, though

2
Duty-Cycling Throughput/Power
Window Length 32ns to 128ns
100kbps/mW
10kbps/mW
Published Results lt 10kbps/mW For 10m
PN Length
3
Transceiver Power Est.
Always On 64ns Window 64ns Tchip 7.1mW _at_ 1.2V
Duty-Cycled 64ns Window 1ms Tchip 3mW _at_ 1.2V
4
Transceiver Operation
RX Parallel Sampling of Window of Time
time
TSAMPLE
TWINDOW
TPULSE_REP
time
TSYMBOL
time
5
Transceiver Controller

• Variable delay from Start From zero to full
  symbol
• Programmable control signals for each block may
  be independently duty-cycled
• Generates ADC control from DLL phases
• Handles post-ADC data realignment and aggregation

6
Example Control Timing
Clk62 enClkIn enGBias enDBias enD sampA enA
Ain Aout Clk3/4 Clk1/4 Clk1/2 ReAligned C
lkP2P ClkDig
1
N/A
B1
B2
1
N/A
N/A
N/A
A1
A2
N/A
N/A
C1
C2
A1
A2
1
N/A
B1
B2
1
N/A
C1
A1
A2
B1
B2
7
Delay Cell Sensitivity

• Fast, Typ, Slow
• 0C, 25C, 50C
• Target Delay 500ps
• dDelay/dVbias
• -4 to 2ns/Volt
• (Tuning range for process variation is 100mV)
• dDelay/dVdd
• 0.05 to 0.375ns/Volt
• (About 1/10 Vbias. Ideally want zero so that
  supply ripple doesnt create jitter.)

8
DLL Worst-Case Deterministic Jitter

• Typ Cond.
• 1.2V, 25C
• 2nH Vdd BondWire
• 40pF Bypass Cap
• Jitter lt 50ps on D32 (settled)
• If disable for 256ns and look at worst-case
  jitter 16ns after re-enable
• lt 75ps jitter
• Thermal Jitter Est. 30ps (stddev)

9
Transceiver Digital Back-End
Process 0.13um (ST Microelectronics) Size 3.3mm
x 3.3mm 245,000 Standard Cells Status In
Place-and-Route Stage