Hardware Part B

1
Hardware (Part B)

• Reading Materials
• Chapter 5 of SG The Computer System
• Optional Chapter 2 of Brookshear
• OUTLINE
• Organization of a Digital Computer
• Major Components of a Computer System
• von Neumann architecture how it fits Together
• The Future non von Neumann architectures

2
Introduction

• Computer organization examines the computer as a
  collection of interacting functional units
• Functional units may be built out of the circuits
  already studied
• Higher level of abstraction assists in
  understanding by reducing complexity

3

• Figure 5.1
• The Concept of Abstraction

4
Digital Computer Logical Organization

• Organization of a Computer

5

• Figure 5.2 Components of the Von Neumann
  Architecture

6
The Components of a Computer System

• Functional units in Von Neumann architecture
• Memory
• Input/Output
• Arithmetic/Logic unit
• Control unit
• Concept of a stored program
• sequential execution of instructions
• One instruction at a time
• Fetched from memory to the control unit

7
Memory and Cache

• The functional unit that stores
• instructions (programs / software) and
• Data / information
• Primary Memory Types
• ROM (Read Only Memory)
• Read only, permanent
• RAM (Random Access Memory)
• Read/Write, Volatile
• Cache memory
• keeps values currently in use (with faster memory)

8

• Figure 5.3
• Structure of Random Access Memory

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Memory and Cache (continued)

• RAM (Random Access Memory)
• Memory made of a large array of addressable
  cells (each of the same size)
• Maps addresses to memory locations (cells)
• Current standard cell size is 8 bits
• All memory cells accessed in equal time
• Memory address
• Unsigned binary number N long
• Address space is then 2N cells

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Memory Unit -- Operations

• Data Transfers
• Need Instructions
• FETCH instr to read content of a memory
  location
• (fetch some data from memory)
• STORE instr to write a value to a memory
  location
• (store some data into memory)
• Need Registers
• MAR for the address of the memory location
• MDR for data to be written to / read from
  memory
• implemented via digital circuitry
• Using decoders to select individual cells
• Fetch / Store decoder

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Registers (or Memory Registers)

• Memory register
• Examples MAR, MDR
• Very fast memory location
• Given a name, not an address
• Serves some special purpose
• Modern computers have dozens or hundreds of
  registers

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The Fetch Operation

• To read data/info from memory
• fetch (address)
• Load the address of the desired memory cell into
  the MAR
• Decode the address in the MAR
• Copy content of that memory location into MDR

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The Store Operation

• To store information into memory
• Store (address, value)
• Load the address into the MAR
• Load the value into the MDR
• Decode the address in the MAR
• Store the contents of MDR into that memory
  location.

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Figure 5.7 Overall RAM Organization
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Cache Memory

• Memory access is much slower than processing time
• Faster memory is too expensive to use for all
  memory cells
• Locality principle
• Once a value is used, it is likely to be used
  again
• Small size, fast memory just for values currently
  in use speeds computing time

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Peripheral Devices (Overview)

• Other Devices that augments the CPUmemory
• I/O Keyboard, mouse, monitor, printers,
  speakers,
• Storage Cache, Disk drives, CD-drive, Zip-drive,
  tapes
• Communication Network cards, modems,
• Devices communicate with CPU via controllers
• usually some kind of circuit board (eg sound
  cards)
• Also,
• I/O devices vary greatly
• Can Dynamically added/removed devices
• Flexible Design needed to allow easy addition /
  removal / upgrading
• Design may be sub-optimal.
• Flexibility often more important than optimality.

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Input/Output and Mass Storage

• Communication with outside world and external
  data storage
• Human interfaces monitor, keyboard, mouse
• Archival storage not dependent on constant power
• External devices vary tremendously from each other

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Input/Output and Mass Storage

• Volatile storage
• Information disappears when the power is turned
  off
• Example RAM
• Nonvolatile storage
• Information does not disappear when the power is
  turned off
• Example mass storage devices such as disks and
  tapes

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Input/Output and Mass Storage

• Mass storage devices
• Direct access storage device
• Hard drive, CD-ROM, DVD, etc.
• Uses its own addressing scheme to access data
• Sequential access storage device
• Tape drive, etc.
• Stores data sequentially
• Used for backup storage these days

20
Input/Output and Mass Storage

• Direct access storage devices
• Data stored on a spinning disk
• Disk divided into concentric rings (sectors)
• Read/write head moves from one ring to another
  while disk spins
• Access time depends on
• Time to move head to correct sector
• Time for sector to spin to data location

21

• Figure 5.8
• Overall Organization of a Typical Disk

22
Input/Output and Mass Storage

• I/O controller
• Intermediary between central processor and I/O
  devices
• Processor sends request and data, then goes on
  with its work
• I/O controller interrupts processor when request
  is complete

23

• Figure 5.9
• Organization of an I/O Controller

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The Arithmetic/Logic Unit

• Actual computations are performed
• Primitive operation circuits
• Arithmetic (ADD, etc.)
• Comparison (CE, etc.)
• Logic (AND, etc.)
• Data inputs and results stored in registers
• Multiplexor selects desired output

25

• Figure 5.12
• Using a Multiplexor Circuit to Select the Proper
  ALU Result

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The Arithmetic/Logic Unit (continued)

• ALU process
• Values for operations copied into ALUs input
  register locations
• All circuits compute results for those inputs
• Multiplexor selects the one desired result from
  all values
• Result value copied to desired result register

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Recap

• Have seen how
• logic gates and flip-flops can be used to form
  combinational and sequential circuits
• Any logic/arithmetic functions (operations) can
  be implemented this way
• But, then the functions will be hard-wired.
• Need a different computer for each new job!!
• Instead, we want a general purpose computer
• computer runs a STORED program
• function of the computer varies according to
  the different STORED program
• the stored program is arbitrary ? general purpose
  computer
• Basic Architecture Von-Neumann Architecture

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The Control Unit

• Manages stored program execution
• Task
• Fetch from memory the next instruction to be
  executed
• Decode it determine what is to be done
• Execute it issue appropriate command to ALU,
  memory, and I/O controllers

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Machine Language Instructions

• Can be decoded and executed by control unit
• Parts of instructions
• Operation code (op code)
• Unique unsigned-integer code assigned to each
  machine language operation
• Address field(s)
• Memory addresses of the values on which operation
  will work

30

• Figure 5.14
• Typical Machine Language Instruction Format

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Machine Language Instructions

• Operations of machine language
• Data transfer
• Move values to and from memory and registers
• Arithmetic/logic
• Perform ALU operations that produce numeric values

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Machine Language Instructions

• Operations of machine language (continued)
• Compares
• Set bits of compare register to hold result
• Branches
• Jump to a new memory address to continue
  processing

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Control Unit Registers And Circuits

• Parts of control unit
• Links to other subsystems
• Instruction decoder circuit
• Two special registers
• Program Counter (PC)
• Stores the memory address of the next instruction
  to be executed
• Instruction Register (IR)
• Stores the code for the current instruction

34

• Figure 5.16
• Organization of the Control Unit Registers and
  Circuits

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Putting All the Pieces Togetherthe Von Neumann
Architecture

• Subsystems connected by a bus
• Bus wires that permit data transfer among them
• At this level, ignore the details of circuits
  that perform these tasks Abstraction!
• Computer repeats fetch-decode-execute cycle
  indefinitely

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Figure 5.18 The Organization of a Von
Neumann Computer
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CPU (Central Processing Unit)

• Components of a CPU
• Control Unit the brain of the CPU.
• decoding which operation is to be performed, and
• deciding the next operation to perform
• ALU (Arithmetic Logic Unit)
• consists of logic circuits for addition,
  multiplication, and all other operations
• Buses wire connecting
• wires connecting up different parts of CPU, and
  the CPU to other components
• Each component is built using logic circuits

38
CPU Execution Example W X Y

• To add two numbers stored in X and Y and store
  the result in W
• CPU performs the following steps

• Place address of first number (X) in MAR
• Issue a FETCH command to Memory Unit
• Transfer content of MDR to Register R1
• Place address of second number (Y) in MAR
• Issue a FETCH command to Memory Unit
• Transfer contents of MDR to Register R2
• Issue a ADD command to ALU to perform addition
  of numbers in registers R1 R2 and place result
  in register R3
• Transfer contents of R3 to MDR
• Place address of result (W) in MAR
• Issue a STORE instruction to Memory Unit

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Functioning of a CPU

• The steps above illustrates
• basic technique for CPU to execute simple
  instructions
• similar technique is used for all other
  instructions
• ANALOGY If we have buttons for the CPU
  functions, then a human can press the appropriate
  button to execute the above step
• In real computers, the
• role of human is performed by the Control Unit,
• role of buttons by using control signals
• Control Unit is also responsible for
• decoding the instruction,
• figuring out the next instruction, etc

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The Future Non-Von Neumann Architectures

• Physical limitations on speed of Von Neumann
  computers
• Non-Von Neumann architectures explored to bypass
  these limitations
• Parallel computing architectures can provide
  improvements multiple operations occur at the
  same time

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The Future Non-Von Neumann Architectures

• SIMD architecture
• Single instruction/Multiple data
• Multiple processors running in parallel
• All processors execute same operation at one time
• Each processor operates on its own data
• Suitable for vector operations

42

• Figure 5.21
• A SIMD Parallel Processing System

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The Future Non-Von Neumann Architectures.

• MIMD architecture
• Multiple instruction/Multiple data
• Multiple processors running in parallel
• Each processor performs its own operations on its
  own data
• Processors communicate with each other

44

• Figure 5.22
• Model of MIMD Parallel Processing

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Summary of Level 2

• Focus on how to design and build computer systems
• Chapter 4
• Binary codes
• Transistors
• Gates
• Circuits

46
Summary of Level 2 (continued)

• Chapter 5
• Von Neumann architecture
• Shortcomings of the sequential model of computing
• Parallel computers

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Summary

• Computer organization examines different
  subsystems of a computer memory,
  input/output, arithmetic/logic unit, and
  control unit
• Machine language gives codes for each primitive
  instruction the computer can perform, and its
  arguments
• Von Neumann machine sequential execution of
  stored programs
• Parallel computers improve speed by doing
  multiple tasks at one time

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• If you are new to all these
• read the textbook carefully
• Do the practice problems and some exercises in
  the book
• Do the tutorials in the course.
• The End