LC3 Datapath

1
LC-3 Datapath
2
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
3
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT

ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
ALU
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
FUNCU
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
4
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
MUXES
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
5
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
CONT
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
6
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
STATE
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
7
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W