The JEPCP backplane Preliminary Design Review

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The JEP/CP backplanePreliminary Design Review
Sam Silverstein, Stockholm University

• Editorial changes, clarifications
• Requested additions
• Controversial items

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Editorial Changes, Clarifications

• Typos, language errors
• 2.4 bullet 3 FIO signals leaving a processor
  module should arrive
• 2.7 par 2 If it becomes desirable for up to two
  VME masters... (Remove up to)
• 3.2, last sentence the, not tbe
• 3.4 M_(740), not (749)
• Appendix C, errors in some signal names

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Clarifications

• 1.1 Overview
• Abbreviation for local VME CPU should be CPU, not
  VME
• Add bullet
• To provide additional pins to the CPU and TCM
  modules for as yet unspecified functions

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Clarifications

• 2.7 Reduced VME bus
• Add
• Modules on the VME-- bus are assigned addresses
  according to geographical address pins (see
  Section 2.9) that uniquely define a modules
  position in the system.
• Clarify single and multiple VME master options
  (controversial)

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Clarifications

• 2.9 Geographical Addressing
• Add at end of paragraph 2
• TCMs in the CP and JEP systems are distinguished
  from those in the pre-processor by an additional
  signal provided by the TCM VME personality card.
• Paragraph 3
• All geographical address lines should be pulled
  up(1) on the modules.

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Clarifications

• 2.10 Power
• Replace last sentence with
• Each module is provided with three high-current
  power pins that carry 5V, 3.3V and power ground
  return. Each pin is rated at up to 40A, providing
  a substantial safety margin for all modules in
  the system.

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Clarifications

• 2.11 Signal Characteristics
• Add
• All line impedances have a tolerance of ?5.
• Controversial?

8
Clarifications

• 3.1 Overview
• Paragraph 3, reference Kithsiris backplane study
  paper (reference?)
• Figures 1-3 Add View from front of crate
• Table 5
• Add current carrying capacity (must research)
• Last line, Ground and cable shields
• Table 6 Add actual pin lengths for custom
  connector

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Clarifications

• Glossary
• CPM Cluster Processor Module
• Processor Module Refers to either the CPM or JEM
• DCS Detector Control System
• HP Unit of module width, 1 HP equals 0.2
• U Unit of module height, 1U equals 1.75

10
Clarifications

• Appendix D
• Connector 1 has long through pins, with shrouds
  in back of plane.

11
Additions

• Add 2.13 Signal Grounding
• The Processor Backplane contains 7 connected
  ground planes that separate the different signal
  layers. Cable connector screens and module ground
  return shields are directly connected to the PB
  ground. Cable signal grounds are not connected to
  the PB ground, but are terminated on the
  processor modules.

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Additions

• Add 2.14 Environmental Conditions
• The Processor Backplane must be able to tolerate
  the following environmental conditions
• Storage Temperature -20C to 85C
• Operating Temperature 0C to 70C
• Relative Humidity 20 to 70

13
Additions

• Specifications for manufacturers
• Have already produced specification documents for
  Bustronic Corporation to obtain quote
• Can include Bill of Materials, PCB specification,
  and PB sketch as additional appendices if desired.

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Controversial items

• VME
• Do we want to have 2 bus masters?
• If so, how?
• Where are arbitration and interrupt lines?
• Grounding of BGnIN in position 1?
• Where is VME bus terminated?
• On adaptor board and TCM, or daughter boards
  behind backplane?

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Controversial items

• TCM and CAN bus
• Extra 5V power on TCM? Where?
• Where is CAN bus terminated?
• Extra 9-pin CAN connector on backplane?
• Where?
• How used?

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Controversial items

• Power and grounding
• Thick bus bars, or separate wires to each module?
• Separate chassis ground plane for cable screens?
• Possible???
• Beneficial?
• How connected to rest of module?

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Controversial items

• CMM pinout
• 75 differential pairs from connectors 4 and 5 to
  daughter card behind backplane.
• Unused pins, especially in connector 8
• Can we use them?
• Do we want to?
• Ground pin distribution

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Controversial Items

• Impedances
• Do we want 60 ohms? Why?
• Is 5 tolerance acceptable?
• TTC signals to CPU positions
• Any objections?
• Review schedule
• Layout review before production?

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Controversial items

• Custom B-19 connectors
• Non-uniform first-make, last-break
• How organized?
• Cost, lead time
• Alternatives?
• Is bracing hardware acceptable?
• Testing in Stockholmwhat is desired?

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Anything I have missed?