CS 6250 Class 12 9.27.2002

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CS 6250 Class 12 9.27.2002

• Switching hardware

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News

• We will discuss problems 25, 26, 29 of chapter-2
  today
• Homework chapter-3, problems 31, 37
• Questions about project?
• Design report is due on Oct 1 (Tue)

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General model of a switch/bridge/router
Input
Output
port
port
Output
Input
port
port
Fabric
Output
Input
port
port
Output
Input
port
port
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Issues in switch design

• Aggregate switch throughput
• For N simplex or half-duplex inputs, each with
  rate C
• Max throughput NC
• What if duplex links?
• Contention packets at multiple inputs headed to
  same output
• Need for packet buffers
• Important factors in switch throughput
• Packet arrival times at each input port
• Output port for each packet
• Packet size
• Bits-per-second and packets-per-second
  bottleneck?
• Blocking vs non-blocking switches
• Scalability in number of ports and port bandwidth
• Cost (and cost-per-port)
• Switch delay is it an issue?

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Input vs output buffering

• Packets may need to be buffered in switch due to
  output port contention
• Input buffering is simplest, but it can lead to
  Head-Of-Line (HOL) blocking
• Important result max throughput in
  input-buffered switch with uniform traffic
  distribution among ports 59 of aggregate
  capacity
• Output queueing does not suffer from HOL but
  requires N times faster memories (N of input
  ports)

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Shared bus architecture

• Simplest switch architecture
• Mostly used in low-end switches/bridges and
  PC-based routers
• Transfer packets between NICs and CPU/memory
  through PCI bus
• PCI bus is often the bottleneck
• Consider 32-bit PCI bus with 33MHz clock
• Maximum throughput 3233 1Gbps
• Can support at most 10 FastEthernet half-duplex
  links
• Suppose all packets are 64B (512b) CPU must be
  able to process 2 millions packets per second
• Higher-end busses today are up to 128b wide,
  running up to 200MHz

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Crossbar switches (with output buffering)

• Dominant switch architecture today non-blocking
• Scales as N2 with number of ports N (ok for N up
  to 32 or 64)
• Crossbar architectures sometimes have input
  buffers, or virtual-output input buffers