PassTransistor Logic

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Pass-TransistorLogic
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Pass-Transistor Logic
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Example AND Gate
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NMOS-Only Logic
3.0
In
Out
2.0
V
x

e
g
a
t
l
o
V
1.0
0.0
0
0.5
1
1.5
2
Time ns
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Transmission Gate
C
C
A
A
B
B
C
C
C
2.5 V
A
2.5 V
B
C
L
C

0 V
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Pass-Transistor Based Multiplexer
S
VDD
GND
In1
In2
S
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Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
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Dynamic Logic
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Lógica Combinacional
Os sinais de saída de um circuito são resultados
de uma combinação lógica dos sinais de entrada
atuais.
Lógica Estática As saídas só mudam de valores a
partir da mudança dos valores de
entrada. Lógica Dinâmica As saídas representam o
resultado da combinação lógica durante um tempo
pré-determinado.
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Dynamic CMOS

• In static circuits at every point in time (except
  when switching) the output is connected to either
  GND or VDD via a low resistance path.
• fan-in of n requires 2n (n N-type n P-type)
  devices
• Dynamic circuits rely on the temporary storage of
  signal values on the capacitance of high
  impedance nodes.
• requires on n 2 (n1 N-type 1 P-type)
  transistors

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Lógica Combinacional
Lógica Dinâmica
Operacão em 2 fases pré-carga avaliação
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Dynamic Gate
off
Mp
Clk
on
1
Out
In1
In2
PDN
In3
Me
Clk
off
on
Two phase operation Precharge (Clk 0)
Evaluate (Clk 1)
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Lógica Combinacional
Resposta a Transientes
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Lógica Combinacional
Porta NAND Dinâmica de 4 Entradas
VDD
Out
In1
In2
In3
In4
f
GND
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Conditions on Output

• Once the output of a dynamic gate is discharged,
  it cannot be charged again until the next
  precharge operation.
• Inputs to the gate can make at most one
  transition during evaluation.
• Output can be in the high impedance state during
  and after evaluation (PDN off), state is stored
  on CL

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Properties of Dynamic Gates

• Logic function is implemented by the PDN only
• number of transistors is N 2 (versus 2N for
  static complementary CMOS)
• Full swing outputs (VOL GND and VOH VDD)
• Non-ratioed - sizing of the devices does not
  affect the logic levels
• Faster switching speeds
• reduced load capacitance due to lower input
  capacitance (Cin)
• reduced load capacitance due to smaller output
  loading (Cout)
• no Isc, so all the current provided by PDN goes
  into discharging CL

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Issues in Dynamic Design 1 Charge Leakage
CLK
Clk
Mp
Out
A
Evaluate
VOut
Clk
Me
Precharge
Leakage sources
Dominant component is subthreshold current
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Solution to Charge Leakage
Keeper
Clk
Mp
Mkp
A
Out
B
Clk
Me
Same approach as level restorer for
pass-transistor logic
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Issues in Dynamic Design 2 Charge Sharing
Charge stored originally on CL is redistributed
(shared) over CL and CA leading to reduced
robustness
Clk
Mp
Out
A
B0
Clk
Me
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Charge Sharing Example
Clk
Out
A
A
B
B
B
!B
C
C
Clk
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Solution to Charge Redistribution
Clk
Clk
Mp
Mkp
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven
transistor (at the cost of increased area and
power)
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Cascading Dynamic Gates
V
Clk
Clk
Mp
Mp
Out2
Out1
In
Clk
Clk
Me
Me
t
Only 0 ? 1 transitions allowed at inputs!
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Lógica Dinâmica
Lógica Dominó
1 ? 1 1 ? 0
0 ? 0 0 ? 1
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Lógica Dinâmica
Lógica Dominó
Características
Lógica não-invertida Muita rápida A adição de
um regenerador de nível de sinal reduz as
correntes de fuga e os problemas de
distribuição de cargas.
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Why Domino?
Clk
Clk
Like falling dominos!
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Properties of Domino Logic

• Only non-inverting logic can be implemented
• Very high speed
• static inverter can be skewed, only L-H
  transition
• Input capacitance reduced smaller logical
  effort

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np-CMOS
Me
Clk
Mp
Clk
Out1
1 ? 1 1 ? 0
In4
PUN
In1
In5
In2
PDN
0 ? 0 0 ? 1
In3
Out2 (to PDN)
Mp
Clk
Me
Clk
Only 0 ? 1 transitions allowed at inputs of PDN
Only 1 ? 0 transitions allowed at inputs of PUN
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Determine a função do circuito abaixo
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Faça o diagrama stick da função

• Y not ((a(bc)def)(ghi))
• Passos para a solução
• Diagrama de transistores
• Caminho de Euler comum aos dois planos
• Fazer o diagrama stick