Network Processing Architectures: An Overview

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Network Processing Architectures An Overview

• Mel Tsai
• 5/31/00

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Network Interfaces

• Intel Internet Exchange Architecture (IXA)
• Common Switch Interface (CSIX)
• Common Programming Interface (CPIX)

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MMC Networks

• nP7120 WAN Networking Processor
• Dual 220 MHz proprietary flow-through RISC
  cores
• Handles packet-over-SONET OC-48c traffic
  (aggregate 2.5 Gbit/s bandwidth)
• Built-in packet policy engine handles packet
  classification and rule-sets

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PixelFusion

• Fuzion 150 Graphics Processor
• Unique SIMD Architecture originally designed for
  graphics but adapted for networking applications
• Central CPU core with an additional 1500 simple
  8-bit processing elements
• 4 independent RAMBUS off-chip memory channels
• Can act as a Layer 2/3 packet parser or a deep
  packet classifier (routing based on packet
  contents)
• Cannot currently support desired 2.5 Gbit/s
  (OC-48), but future version will support CSIX
  (Common Switch Interface) and 10 Gbit/s (OC-192)
  bandwidth

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SiTera

• Prism IQ2000 Network Processor Family
• Four proprietary RISC cores each running at 200
  MHz. Package is 673 pins, 7 watts. 256Kbit
  on-chip SRAM.
• Multivariate packet header processing, not
  intended for general system control, requires
  external coprocessor
• Multiple hardwired engines for multicast
  management, table lookup, context control, DMA,
  QoS priority management, and RED.
• 50 Gbit/sec internal streaming FusionBus.
• External proprietary FocusBus I/O Interface
• Intended for midrange OC-3 to OC-48 applications

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EZchip

• EZSwitch OC-192 10 Gbit/sec Network Processor
• 2nd Generation network processor
• 40 small processing engines, each specially
  pipelined and designed to perform either packet
  parsing, searching, packet modifying, or packet
  resolution.
• Engines work in parallel to achieve uninterrupted
  OC-192 service.
• 0.18 micron process, designed to forward a packet
  in under 60ns.
• Each search engine given separate embedded DRAM
  block connected with a 512 bit bus.
• Up to 128 EZSwitch processors on a single
  backplane

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Fast-Chip

• PolicyEdge Packet-Classification Network
  Processor
• Classifies up to 10 million packets/sec
• Database-oriented internal hardwired structure
  with proprietary arithmetic memories (BAMs
  boundary-addressable memories), fast on-chip
  table lookups, and a SiTera FocusBus compatible
  interface.
• Designed to handle differentiated services, QoS
  management, and VPN secure tunneling.

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Lucent

• Agere Network Processing Family
• NPSRP PayloadPlus Routing Switch Processor
• OC-48c speeds
• Handles QoS Packet Management
• Works in conjunction with the Agere FPP packet
  classifier and the Agere ASI packet policy
  manager.

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Solidum

• Pax.port family of packet classification cores
• Supports OC-48 and soon OC-192 speeds
• Uses the Pax Pattern Description Language
• Similar to the Lucent Agere family and the
  NeoCore packet classification engines.
• Uses a programmable state machine instead of CAMs
  and SRAMs, avoiding junk bits and allows packet
  classification to defy Moores law.

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Solidum (cont.)
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Zilog

• Cartezian Communication Engine
• Tensilica-based implementation, ships as a soft
  core
• Contains a 200 MIPs synthesizable RISC core with
  multiple 150 MIPs edge processors

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Other Players

• Motorola C-Port C5
• Similar to SiTera PRISM Network Family
• IBM Rainier PNP (Power Network Processor)
• Centralized PPC with multiple PicoProcessors
• Foundation for many new network processor designs
  from other companies
• SwitchOn Networks Inc
• ClassiPI Content-Switching Network Coprocessor
• BRECIS Communications
• Entridia
• Opera family of high-speed ASIC OC-768
  hardwired edge routers
• PMC-Sierra Aal1gator ATM Processors
• Intel IXP1200