Sun Microsystems Clinic 19992000

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Sun Microsystems Clinic1999-2000
GrandSun of MacTester
Final Presentation April 25, 2000
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Sun Microsystems

• Were the dot in .com
• Develops and builds high performing workstations
  and servers
• Developed the JAVA programming language
• Designs and builds chips

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Functional Chip Tester

• Feeds inputs to a device under test (DUT)
• Reads outputs
• Checks if results are as expected
• Standard tester is expensive

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Sun of MacTester Specs

• Operates the DUT from 1 to 7 Volts
• Tests packages with up to 132 pins
• Interfaces with PCs, Macs, and Suns

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Sun of MacTester Data Flow
Daughter Card
Software Interface on Host Computer
Host to Peripheral Interface
Master Controller
(Serial Port)
(PC Software)
DUT Socket
Serial/ Parallel Converter
Parallel Communication
Input Voltage Converter
Serial Communication
DUT Pin
Output Voltage Converter
Main Board
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Drawbacks of Sun of MacTester

• Cannot test devices with more than 132 pins
• Trace lengths
• Large package size
• Connector reliability

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Problem Statement

• The goal of this project is to construct a
  robust, compact, inexpensive, and easy to use
  functional tester supporting tests of devices
  with up to 256 pins, operating on supply voltages
  from 1 to 7 volts, suitable for use by Sun Labs
  and by universities.

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GrandSun of MacTester Specs

• Tests devices with up to 256 pins
• Operates device from 1 to 7 volts
• Short traces between pin electronics and DUT
• Robust mechanical connectors
• Interface with Suns and PCs
• Easily accessible pin electronics and daughter
  card
• Finished packaging

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Chip Tester Differences

• Sun of MacTester
• 132 DUT pins
• Slave FPGAs/ Comparators
• 18 x 18 x 4

• GrandSun of MacTester
• 256 DUT pins
• Custom Pin Electronics
• 5 x 7 x 4

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GrandSun Data Flow

Interface
Host Computer
Main Board

PinDriver Card
PinDriver Electronics
Master Controller
Main Board Connectors
Parallel Communication
Daughter Card
Device Under Test
Serial Communication
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Main Components

• Main Board
• PinDriver Card (PDC)
• Daughter Card

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Main Board

• Master FPGA
• Controls operations by routing data and commands
• Communicates with the host via RS-232 UART

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PinDriver Card

• Communicates with Main Board in serial
• Communicates with Daughter Card in parallel
• Performs voltage conversion
• One PDC tests up to 64 pins

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Daughter Card

• Holds the DUT with a Zero Insertion Force (ZIF)
  socket
• Allows for multiple package types
• Header pins for DUT pins, Vext, and GND

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Packaging

• Contains Main Board and four PDCs
• Daughter Card is external
• Package mount LEDs, reset button, and power
  switch
• External power supply

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Deliverables

• Two testers to Sun Labs
• One tester for use at HMC
• Daughter Cards (40 pin 256 pin)
• Final Report
• Software Manual and Daughter Card Guide
• Test Results

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Budget

• Board Manufacture 92
• Custom Electronics 95
• Off-the-Shelf Electronics 90
• Travel and Meals 114
• Supplies 19
• Total 92

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Acknowledgments
Team Members April Fields (Team Leader) David
Honeycutt Ronalee Lo (Spring 2000) Stephani
Ordinario Tina Wang (Fall 1999) Robin Willingham
Advisor Prof. David Harris Liaisons Ian
Jones Jon Lexau Jonathan Gainsley 99
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Master FPGA

• UART/USB initialization
• Set DUTs for high Z
• Wait for test initialization
• Load test onto slaves
• Apply test to DUT
• Read DUT output and Latch
• Transmit to interface

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PinDriver Card

• Each card is capable of testing 64 pins on the
  Device Under Test (DUT)
• Drives test vector data to and samples output
  data from the DUT pins in parallel
• Receives and sends inputs and outputs to the Main
  Board in serial

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Scan Chain
sample
drive
ph1
ph2
sdin
din0
dout0
en0
dout255
din255
en255
sdout
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Single Pin Logic
sample
ph1
ph2
drive
sdin
dout
D
D
D
Q
Q
Q
din
enable
D
D
D
Q
Q
Q
sdout
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Testing

• Initially, perform walking ones chip test (just
  in case it actually works)
• Next, go through hardware debugging stages
• Wire Chip Test
• Real Chip Test

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Walking Ones

• Sets one pin high at a time
• Checks that pin INPUT matches pin OUTPUT when the
  pins are not connected together
• Also, checks that all other pins remain low
• Can therefore Determine
• If any pins are tied together
• If output circuits are not functioning properly
• Used by last years team

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WireChip Test

• Can be used to check that PinDriver and daughter
  card circuitry work
• By inserting it in different directions,
  different tests can be run
• Software is used to determine results

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Stages of Debugging

• Check communication with host and UART (send one
  byte, receive one byte test)
• Ensure (proper) configuration of all FPGAs
• Make sure FPGA configures serial port correctly
• Check control signals to PinDriver card(s)

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Tester 0.0
Daughter Card
MainBoard
Pin Electronic Cards
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Rev 0.0 Data Flow
MainBoard
Interface
Host Computer
Pin Driver Card
Master Controller
Main Board Connectors
PinDriver Electronics
Parallel Communication
Serial Communication
Daughter Card
Device Under Test
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Revision 0.0

• Reduce overall size of tester
• Increase number of testable pins
• Use Slave FPGAs to stand in for Custom Pin
  Electronics Chips

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Revision 0.5

• Replace Serial interface with USB
• Change data flow to be more intuitive
• Change physical layout of tester for new data
  flow
• Replace Slave FPGAs with Custom Pin Electronics
  Chips
• Package tester
• Fix bugs found in revision 0.0

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Revision 1.0

• Fix bugs found in revision 0.5

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MainBoard 0.0--Components

• Interface--communicates with host computer
• transceiver
• crystal oscillator
• serial port connection
• Master FPGA--control all operations
• EPROM--programs the master FPGA
• Clock Oscillator
• Power Supply Connection
• Connectors to PinDriver cards and daughter cards
• LEDs--ERROR, High Z (safe), Power ON
• RESET
• Vext--sends reference voltages to PinDriver cards

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MainBoard 0.5

• Replace Serial Interface with USB
• Replace Daughtercard Connectors
• Find way to secure Pin Electronics Cards
• Fix Problems
• Increase Daughter Card Pitch

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USB Interface

• Up to 12 MB/s
• Easily obtainable microcontroller
• Data transmission sequence
• Initialization process

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Revision 1.0
connector
custom chip
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Revision 0.0 and 0.5
connector
FPGA
EPROM
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Daughter Card
Input data to pins from MainBoard
Device Under Test (DUT)
Output data from pins to MainBoard
Vext and current
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Ver. 0.0 - 40 pin Daughter Card

• ZIF socket
• Connector pads
• 3 layers top signal, bottom signal, GND
• Traces to route Vext
• Header pins for power housing
• Header pins for Vext, Pin, GND
• Various alternating capacitors

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Ver. 0.5 - Planned Changes

• 128 pin daughter card
• larger ZIF socket
• layout?
• Different connectors
• 3 layers vs. 4 layers?

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Data Flow for 0.0
MainBoard
Interface
Host Computer
Pin Driver Card
Master Controller
Main Board Connectors
PinDriver Electronics
Parallel Communication
Daughter Card
Device Under Test
Serial Communication
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Dummie Boards

• Test connector configurations
• Investigate connector reliability and alignment
  issues
• Help evaluate better data flow options
• Test USB

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Dummie Results

• Some connectors were not robust
• Edgecard connectors held up the best and were
  easiest to use for all of our purposes

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House of Cards

• Order of assembly
• PinDriver cards come out with daughter card
• PinDriver cards do not come out of packaging
• Pin Electronics Protection
• plastic
• metal

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USB Performance

• 12Mb/s in high speed bulk transfer
• Hot pluggable
• Numerous peripherals
• Can be ported to PC, Mac, Sun with a single
  connector type
• Runs error check

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USB Properties

• NRZI - Non Return to Zero Inverted encoding
• Four operation modes - Isochronous, Interrupt,
  Control, Bulk(fastest)
• Multiple reserved endpoints (registers)

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System Requirements

• USB Peripheral Control Chip
• Central Controller (master FPGA)
• USB ready computer
• USB port
• USB libraries (C)
• Software

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Hardware Options

• Intel chip - More ability than we need, too
  complex
• Anchor EZUSB - Really poor documentation
• Mitsubishi - Also poorly documented
• Phillips PDIUSBD12 - 28 pins, small amount of
  firmware

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PDIUSBD12 Specs

• Bulk transfer of 8Mb/s actually achievable
• Programmable clock with 6MHz input
• SIE - Serial Interface Engine built in
• No transceiver required
• SoftConnect and GoodLink
• 8KV in circuit ESD

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Software Requirements

• Win 98
• Built in drivers
• Port description
• Device detection and description
• Interrupt Servicing
• Read/Write

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Send a Byte Plan

• Software up to send a byte
• Hardware on dummy
• Micro-ps FPGA
• FSM through read a byte

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Expansion

• Complete low level software
• Update current software mid and high level as
  necessary
• Overlay USB config FSM and tester function FSM
• Update boards as necessary

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Slave FPGA PinDriver Card
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Custom MOSIS Chip

• Replaces slave FPGAs, CMOS switches, and quad
  comparators on last years tester
• Converts voltage level from 5V to 1-7V
• Stores and transfers data
• One chip drives 64 Device Under Test pins