Final Project Report Multipliers and Adders

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Final Project ReportMultipliers and Adders

• John Ogembo
• Zach Smith

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Outline

• The multipliers and adders
• Goals and Specifications
• Design Process
• Simulation and Timing Diagrams
• Achieved Design Specification
• Conclusion

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Multipliers and Adders

• Spatial Filter
• Correlator
• Matched Filter

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Spatial Filter

• No pipelining
• Includes two multipliers with overflow detect

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Multipliers and Adders

• Spatial Filter
• Correlator
• Matched Filter

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Correlator

• Includes two 8 by 1 multipliers, 2s complement
  form
• Two 8-bit adders
• Three pipelining registers

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8 bit adders
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Multipliers and Adders

• Spatial Filter
• Correlator
• Matched Filter

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Matched Filter

• Four 8 x 8 multipliers
• Two adders with overflow detect
• Three pipelining registers

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Adders 16 bit overflow
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Goals and Design Specifications

• Working chip
• Target speed 100 MHz
• Fixed point integer
• 2s complement format wherever signed numbers are
  used
• 16 bit vector Complex Numbers for Matched Filter

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Design Process

• 4 Multipliers
• 2 Adders
• 5 pipelining registers

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Initial Multiplier Design

• Advantages
• Size, power
• Disadvantages
• Slow
• Multiple clock cycles to perform operation
• Complicated to debug

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New Multiplier Design

• 8 bit input Multiplier
• Single cycle
• Uses Cells
• To take care of overflow, an overflow detector
  was added as shown below

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Multiplier Signal propagation

• Signal propagates all the seven cells
• Signal take .61ns in each cell

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Cell Timing

• Timing diagram of a single cell

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Multiplier Timing Diagram

• This is the worst-case scenario timing of the
  multiplier,
• 01111111
• x 01111111
• This takes 9 ns

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8 bit Adder

• Implemented using carry look ahead
• This eliminates the carry delay speeding up
  addition

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Addition Problem

• Problem It is impossible to tell the sign of any
  output from the adder. This is needed to
  determine the sign of the default overflow output
• Solution Use logic based on the inputs and
  outputs to determine the sign of the output

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Addition Problem (example)

• Notice
• 0000
• 1110
• 1110

0111 0111 1110
0 (-2) -2
7 7 14
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Adder With Overflow

• This adder performs
• if S gt 0111,(max)
• S 0111 (7)
• If S lt 1000 (min)
• S 1000 (-8)

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Substractor Timing Diagram

• Worst scenario
• Operation of (-1)-(-1) 0
• This takes 7.8 ns

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Small

• 2 x 8 bit input
• 8 bit output
• 12 test pins

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Flat

• Same as previous, flattened
• Used for layout

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Layout

• Reduced design layout

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Padframe

• Padframe for our design
• Utilizes 39 pins with one pin with no connection.

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Achieved Design Specification

• Clock speed of 100 MHz
• Correctly multiplies signed, fixed-point, complex
  integers.

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Conclusion

• Correct functionality of the overall design and
  its clear verification is crucial to progress on
  the project.
• The theoretical results remain tentative until
  simulations can verify that the design meets
  specifications.
• DRC and LVS verification was performed on the
  layout and both passed this initial test thereby
  verifying the correct-to-spec functionality of
  the design.

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Questions

• Pad frame DRC check
• How to implement hierarchical automated layout