A Switch Level Fault Simulation Environment

1
A Switch LevelFault Simulation Environment

• Venkatram Krishnaswamy
• Jeremy Casas
• Thomas Tetzlaff
• Intel Corporation, Hillsboro, OR

2
Overview

• Need for switch level capability
• Fault injection techniques
• Fault Simulation Algorithms and Performance
• Mixed Level Fault Simulation
• Conclude

3
Motivation for Switch Level

• Cost of creating gate level database
• remodeling effort, library maintenance
• Accurate fault location for defect based test
• Piggy back on other design activities for tuned
  circuit database
• Formal Verification
• Dynamic Verification
• Challenge is to make it feasible to manipulate
  more information at reasonable cost

4
Related Work

• Gate level fault simulation
• Concurrent algorithms (Ulrich et al)
• Differential algorithm (Cheng et al)
• PROOFS (Niermann et al)
• Switch level fault simulation
• Switch level concurrent (Schuster et al)
• Switch level PROOFS (Vandris et al)

5
Stuck Fault Injection
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Transition Fault Injection
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Transition Fault Injection
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Transition Fault Injection
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Fault Injection Strategy

• Flexibility
• stuck fault model
• transition faults
• bridging faults
• Efficiency
• minimize simulation overhead

10
Fault Simulation Overview

• Perform good machine logic simulation for each
  vector
• save state of the machine
• Faults are injected
• initial states of faulty machines are restored
• Faulty machines are simulated for the given
  vector
• final states of machines analyzed
• Differences in state between good and faulty
  machines need to be computed and stored for use
  with following vector

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Fault Simulation Algorithm Specs

• Capable of simulating complex circuit styles
• domino, self timed precharge, freq.
  Multiplication
• Minimize faulty machine simulation overhead
• Minimize state manipulation overhead
• Exploit word level parallelism

12
Problems posed by switch level fault simulation

• Massive number of sequential nodes
• recirculating feedback
• capacitive nodes
• Support of certain circuit styles is costly as
  they require unit delay simulation algorithm
• precharge-discharge circuits
• self timed precharge
• clock frequency multiplication

13
Underlying logic simulation models

• Circuit Model (ref COSMOS - Bryant et al)
• ternary logic value model 0,1,X
• transistor strength modeling
• capacitance modeling
• Delay Model
• unit delay model
• devices can be selected to be zero delay

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Unit Delay Fault Simulation Algorithm

• PROOFS style algorithm requires faulty machine
  simulation after every unit step of logic
  simulation
• Overhead of faulty machine state manipulation
  dominates runtime at switch level
• Cheaper to completely relax good machine and
  faulty machines separately
• downside is recomputation of events in good
  machine

15
Optimization of State Manipulation

• Aim is to minimize value copying to and from
  simulation data structures
• State differences between passes are maintained
  with respect to the last simulated pass.
• First fault pass differences computed w.r.t good
  machine
• Second fault pass differences computed w.r.t
  first fault pass
• Complicates fault dropping and reordering

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Simulator Performance Analysis

• Figure of merit is Fault Hertz
• computed as (faults cycles)/cpu seconds
• Factors contributing to high Fault Hz numbers
• fast underlying logic simulator
• efficient state manipulation
• Good indication of algorithm scalability

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Performance of Fault Simulator

• Performance improves with increasing number of
  faults
• improvement tails off after 400-800 faults for
  unit (100,000 transistors)
• Full chip Pentium II runs at about 26 fault
  Hertz
• Memory performance is good given large number of
  differential states

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Optimizing Fault Simulation Algorithm

• Attempt to minimize fault passes
• use concept of active modules
• only fault passes with active modules are
  simulated
• Dynamic regrouping of fault passes
• faulty machines are periodically regrouped
• idea is to eliminate faulty passes with one or
  two active machines.
• Performance improvement ranges from factor of 2
  to 4
• PentiumII now simulates at 40 fault Hertz

19
Mixed Level Fault Simulation

• Seed faults in blocks modeled at switch level
• Propagate fault effects to POs using RTL model
• leverage performance of RTL simulation
• Communication between simulators through APIs
• RTL simulator runs as master

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Mixed Level Simulation Issues

• Determination of signal strengths
• drive strength information is compiled in model
• insert structure to determine strength to
  communicate across simulation APIs
• Resolution of multiply driven nodes
• drivers may reside across switch level and RTL
• Performance better than commercialgate level
  simulator in mixed level environment running
  PentiumPro
• Fault Hz ranges between 45 and 200 Fault Hertz

21
Conclusions

• Advantages of using switch level model
• Presented techniques for handling problems posed
  by switch level fault simulation
• efficient state manipulation
• unit delay tradeoffs for precharge-discharge
  circuits
• Simulation speed is not lost through the use of
  mixed level simulation