ASTER Ingnierie

1
ASTER Ingénierie
February 6, 2002 - Mr. Christophe LOTZ

• TESTWAY
• Test Point Saver

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Context

• Why? Because of the dramatic increase in device
  density on PCB.
• What for ? To reduce the number of required Test
  Points whilst still maintaining a high level of
  fault coverage.
• How? TestWay includes
• A test efficiency analysis according to test
  access, either identified at the layout stage or
  declared at the schematic capture stage.
• A proposal to reduce the number of test points
  required to achieve good fault coverage.
• A proposal to increase test efficiency by adding
  a limited number of test points.
• Cluster identification define device groups to
  be tested together using a reduced number of test
  points.

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Accessibility

• In most of design cycles, test access is chosen
  after the layout phase. It is calculated
  according to physical constraints such as pad
  sizes, vias diameter, tracking
• As one physical access per net is no longer
  possible, a virtual access can be used to keep an
  acceptable fault coverage.

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Accessibility

• Using a Virtual channel
• A net is testable when a logic state can be
  assigned through one channel and the result
  observed by a second one.
• Up and down stream chains must be designed so
  that signal propagation is easy (Boundary-scan,
  serial resistor, ).

5
Interconnect Test Analysis

• The ITA module performs net classification in
  order to allocate each a priority level for test
  access.
• TestWay identifies extra test points which could
  be removed. It also suggests design modifications
  that would reduce the test points requirements.

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Interconnect Test Analysis

• Ground nets

• Power nets

• Unused pins

• Pins only connected to a
• pull resistor

• Pure Boundary-Scan nets

TDI
TDO
TDI
TDO

• Partial Boundary-Scan nets

• Tester access

Vcc

• Non-scan nets with no tester
• access

Vcc
TDI
TDO
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Interconnect Test Analysis

• Define you test access requirement using
• Group or Sub-Group
• Class or Property
• Device
• Pin
• Net
• Custom Rules

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Device Test Analysis

• The DTA module verifies each device based on
  overall test access. The theoretical test
  efficiency may be given by the following formula
• Coverage

number of testable pins
number of pins
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Device Test Analysis

• The DTA module identifies clusters when
  partitioning the board into independent
  functional blocks.
• A cluster is a block of devices tested as one,
  using one set of test vectors and limited access.
• Internal access to this block is not essential
  for high fault coverage.
• Device type analysis is an important parameter
  when defining easily testable clusters.
• Boundary-scan clusters have some of their access
  points connected to partial boundary-scan nets.

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Device Test Improvement

• The DTI module tries to improve the coverage by
  adding a limited number of test access points.
• Best order to increase the coverage step by step
• Customer driven objective using device reference
  or classes.

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At layout level
Electrical View
Physical view
TestWay
Test point locations
Check fault coverage according to the real
physical accesses.
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At schematic level
Electrical View
Physical view
TestWay
Select the absolutely required test access points
to guarantee a good fault coverage.
Test points required
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Combined approach
Electrical View
Physical view
Schematic Capture
Layout
CIM
TestWay
Test points required
Test point locations
Check the required test accesses versus real test
point locations.
Fault coverage report
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Cost saving on fixture

• If you save 30 of Testpoints per fixture
• Nail 100 mils US 3.5
• 50mils US 10
• Fixture 2000 nails (100 mils) 3.5 7000
• 200 nails (50 mils) 10
  2000
• 9000
• . Save around 2700 per fixture