Running a Quantum Circuit at the Speed of Data

1
Running a Quantum Circuitat the Speed of Data

• Nemanja Isailovic, Mark Whitney, Yatish Patel,
  John Kubiatowicz
• U.C. Berkeley
• QEC 2007

2
The Impact of QEC
Data Involvement in QEC Step
H
Zero Ancilla Prep
Zero Ancilla Prep
Zero Ancilla Prep
time
3
The Speed of Data

• Non-Transversal Logical Gate
• Zhou et al., Phys. Rev. A, 62(5)52316
• Ideally, execution time determined solely by data

Non-Transversal Ancilla Prepare
4
Limited BW Graph

• 32-bit Quantum Carry-Lookahead Adder in Ion Traps
• Varying rate at which encoded zero ancillae are
  provided for QEC
• Conclusion design architecture with ancilla
  factories

5
Idealized Qalypso Architecture

• Dense data region
• Data qubits only
• Local communication
• Shared Ancilla Factories
• Distributed to data as needed
• Fully multiplexed to all data
• Output ports ( ) close to data
• Input ports ( ) may be far from
• data, since recycled qubits have
• irrelevant state
• Goals
• Design ancilla factories
• Answer Question How much hardware is needed for
  ancilla generation to run at the speed of data?

6
Our Quantum CAD Toolset

• Automated toolset to assist in architecture
  design
• Ion trap technology
• Local gates two qubits in the same trap
• Basic block abstraction to avoid unknown
  electrode details

Dr. Hensinger, University of Sussex
3-way intersection

• Our basic layout blocks

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Level 1 7,1,3 QEC Circuits
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Zero Ancilla Factory Design I

• In-place ancilla preparation

• Ancilla factory consists of many of these
• Encoded ancilla prepared
• in many places
• But we want input and
• output ports

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Zero Ancilla Factory Design II

• Pipelined ancilla preparation break into stages
• Match physical qubit bandwidth between stages for
  high utilization
• Steady stream of encoded ancillae at output port

Physical 0 Prep
CNOTs
Verif
X/Z Correct
Cat Prep
Junk Physical Qubits
Good Encoded Ancillae
Crossbar
Crossbar
Crossbar
CNOTs
Physical 0 Prep
X/Z Correct
Cat Prep
Verif
Recycle cat state qubits and failures
Recycle used correction qubits
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Area Needs for Ancilla Preparation
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Practical Qalypso Architecture

• Multiple Data Regions
• Each serviced by local ancilla factories
• Communication network moves data between regions
  (not shown)
• Data regions as large as possible to get benefits
  of minimizing inter-region movement and
  multiplexing ancilla factory output

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Summary

• Investigated removing ancilla generation from
  critical path
• Operations on data qubits dictate performance
• Tradeoff in ancilla bandwidth vs execution speed
• Architectural approach ancilla factories
• Match production bandwidth to needs of data
• Pipelining places output ports close to data
• Qalypso architecture
• Dense data regions with local communication
• Ancilla factories segregated from data
• Multiplexing between factories and data
• Input and output ports
• Layout investigation gt ancilla generation
  dominates area