NBTIAware Synthesis of Digital Circuits

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NBTI-Aware Synthesis of Digital Circuits

• Sanjay Kumar
• Chris Kim
• Sachin Sapatnekar
• University of Minnesota
• DAC 2007 Session 20.3

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Negative Bias Temperature Instability (NBTI)
Vdd
Relaxation
Stress
S
G
VG Vdd
VG 0
Increase in PMOS Vth gradually over a few years
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Outline of this talk

• Problem Description
• How does NBTI affect circuits?
• Modeling and Estimation
• What parameters does it depend on?
• Design for Reliability
• How can we overcome this effect?
• Results and Summary
• How does our work compare with other solutions?

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Problem Statement
NBTI in PMOS devices
Aging - circuits become slower
Operate circuits at lower speeds
NBTI-aware robust circuit design
Design NBTI-resilient circuits with the least
amount of overhead
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Sizing for Reliability DATE06, ICCD06, ISQED07
After 10 years
Original design
Gates become weak, target freq not met
Area overhead
Reliable design
After 10 years
Design sized accounting for aging
Still meets specs
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Worst Case NBTI Assumption

• Worst case NBTI
• All PMOS devices degrade maximally
• Easy to estimate impact
• Conservative and pessimistic

• Actual Circuit Operation
• NBTI effect based on Signal Probability (SP)
• Each node has a certain SP
• Worst case can never happen

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Limitations of Sizing based flow
Sizing
10 years aging
Nominal Timing Spec T0 ps.
New Timing Spec 0.91T0 ps.
10 delay increase
Allows changes in gate sizes only
Synthesize circuits accounting for NBTI-induced
delay degradation.
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Our Work

• Requirements
• NBTI-aware library characterization
• Signal probability of primary inputs
• Suitable cost function (delay, area, power, etc)
  in tech-mapping

• Focus
• Incorporate NBTI-guard banding into synthesis
  during tech-mapping
• Reduce pessimism in estimation of aging effects
• Design best NBTI tolerant structures

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NBTI Modeling and Library Characterization

• Key Results

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NBTI Model (ICCAD06)
Vdd
0
PMOS under Stress Interface trap generation NIT
increases as t(1/6)
PMOS under Relaxation Annealing of existing
traps NIT decreases

• NIT strong function of Signal Probability (SP)
• Electrical parameter ?Vth NIT

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Vth Degradation
Vdd
Vdd
0
Vthmax
Signal Probability Probability that the signal
is low
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Inverter Characterization
Build a model of delay versus signal probability
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NAND Gates
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NOR Gates PMOS Stacking
B
A
B
A
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Technology Mapping

• SiS synthesis tool
• 42 gates (NOT, NAND2, NAND3, NOR2, NOR3, AOI12,
  AOI22, OAI12, OAI22)

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Nominal Synthesis
Library Delay of gates characterized assuming no
NBTI (Nominal PMOS Vth)
Logic cone Boolean function realized at each node
Cost function Minimum area that meets the target
delay
Compute delay of different candidate blocks at
each node
Choose the structure with the best cost function
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NBTI-Aware SP-based Synthesis
Library Delay of gates characterized for each
signal probability
Library Delay of gates characterized assuming no
NBTI (Nominal PMOS Vth)
Logic cone Boolean function realized at each node
Cost function Minimum area that meets the target
delay
Logic cone Signal probability propagated from
PIs to all nodes in subject graph
Compute delay of different candidate blocks at
each node
Choose the structure with the best cost function
Pick best candidate gate under a new metric for
delay
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Subject Graph
NAND-NOT Dual Representation of the Subject Graph
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Performing SP-based Synthesis
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Performing SP-based Synthesis
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Performing SP-based Synthesis
Pushing nodes with large SP inside the gates
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Worst Case Synthesis
Pick best candidate gate under worst case
NBTI-induced delay
Library Delay of gates computed using Vthmax for
PMOS transistors
Logic cone SP of each node in subject graph set
to 1
Cost function Minimum area that meets the target
delay
Choose the structure with the best cost function
Compute delay of different candidate blocks at
each node
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C17 - Synthesis Results
Increasing size
Tspec 70ps
Circuit fails with aging
Nominal synthesis Area 7.4µm
Worst case synthesis Area 11.6µm
SP-based synthesis Area 9.8µm
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Temporal Degradation of Circuits
Data for Benchmark C432
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Area Delay Curve Benchmark b1
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Overall Savings
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Distribution of Gate Types Benchmark des
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Summary

• NBTI (aging) in circuits causes delay degradation
• Need to relax timing or design NBTI-resilient
  circuits
• Area increase to counter effect of Vth
  degradation
• NBTI-aware optimal synthesis method presented
• Signal probability based design reduces
  pessimism, leads to area savings over worst
  case methods

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Thank You

• Questions and Comments

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Backup
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Synthesis versus Sizing
Which one is better?
Spec
Delay
Area
Target lifetime (log scale)
Time of operation (log scale)
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What if

• Signal Probability (SP) of primary inputs not
  equal to 0.5
• SP values closer to the worst case

• Gain over worst case depends on library gates,
  sizes and SP distribution
• Still better than sizing approaches
• Can we set SP such that gain is maximized?

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C17 Synthesis with Different SP
Increasing size
Tspec 70ps
0.8 SP-based synthesis Area 10.8µm
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Converting Random Waveforms to Deterministic
Periodic Signals
(SP, AF)
Interface trap count for both these
waveforms are equal asymptotically
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Frequency Independence
Vdd
freq f1
T1
n1 cycles
Vdd
freq f2
n2 cycles
T2
Number of interface traps for both cases
same Trap generation independent of frequency
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sk Notation Multi-cycle Model
Vdd
q-p
p
p/q SP
q
0 lt i p
NIT(kt0) sk NIT(t0)
sknqi
p lt i q