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R

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Devise an architecture for the DAQ system. Acquire knowledge and experience with ... Joint URD for Alice/LHCb (finished) Hardware interface URD (need SD input) ... – PowerPoint PPT presentation

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Title: R


1
RD Plan for ECS/DAQ
  • LHCb Plenary Meeting
  • 18 June 1998
  • Beat Jost Cern/EP

2
Outline
  • Project Phases
  • RD Goals
  • Activities and Schedules
  • Summary

3
Project Phases
4
RD Goals
  • Devise an architecture for the DAQ system
  • Acquire knowledge and experience with potentially
    applicable technologies to solve the problems
  • Assemble small scale hardware prototype (String
    Test) running at full speed to exercise ideas
  • Make an educated decision on the technologies to
    use for the implementation of the final system

5
Activities
  • Architecture and protocol design
  • Controls (ECS)
  • Joint Project to devise a common controls kernel
    for all LHC experiments and all aspects of
    control
  • Event Filter Farm (Joint Project)
  • Study management of large and data flow processor
    farms
  • Mass Storage (Joint Project)
  • Study limits of mass storage technology

6
Activities (2)
  • Readout Unit Project (H. Müller)
  • Study implementation of RU
  • Event Building Project (J.-P. Dufey)
  • Devise an event building strategy and study
    possible technologies
  • Timing and Fast Control (TTC) (NN)
  • Study implementation of the fast control
    architecture (Readout Supervisor, etc)
  • Front-End Multiplexer (NN)
  • Study FEM implementation

7
Controls Sub-Projects
  • Selected Controls Sub-Projects
  • Joint URD for Alice/LHCb (finished)
  • Hardware interface URD (need SD input)
  • Architecture design (ongoing)
  • Technology survey (finished)
  • CANbus evaluation (ongoing)
  • OPC evaluation (starting after summer)

8
Schedules
9
Summary
  • RD Phase to last until beginning of 2002
  • There are quite some activities being launched,
    either as joint projects with other LHC
    experiments or within LHCb
  • We still need quite some effort at board level
    design for the TTC sub-system and the FEM
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