PowerPointpresentasjon

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ALICE week Sep 2001- PHOS meeting
PHOS FrontEnd and Readout Electronics (B.
Skaali a walk-through) The PHOS milestones
PHOS ReadOut chain general structure H/W
design, baseline and extended Communication
with ALICE DAQ Communication with ALICE Trigger
H/W components status Resource
situation Requirements and action list
Installation also later presentation by
Klovning
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PHOS milestones

• Milestones, as presented to the LHCC Jan 2001

Final design of PIN preamp 06/2000 - Reached
Final design of read-out electronics -
09/2002 Assembly of the first PHOS module
12/2002
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The PHOS ReadOut Chain

• Baseline version
• no PHOS trigger
• no TOF capability
• no High Level Trigger
• FE MEB processing
• data structuring
• zero suppression
• cluster finder ?
• leaving PHOS territory
• shipping events over Digital Data Link to ALICE
  DAQ system

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The PHOS ReadOut Chain Ext

• Extended version
• PHOS high pT trigger
• adding circuitry, PHENIX?
• TOF capability
• 1 nsec timing resolution, requires modification
  of preamplifier
• input to HLT ?
• who knows ?
• interaction with CPV and LED monitoring system
• anything more?

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PHOS ReadOut Chain lt-gt ALICE DAQ

• FEE interaction with ALICE DAQ system
• Hardware requirement
• ALICE Digital Data Link (DDL) Source Interface
  Unit SIU
• Bus connection
• Board space
• Protocol requirement
• DDL protocol at SIU level
• FPGA
• Transfer on Trigger L2accept
• Exploitation of DDL duplex functionality for
• download of control code
• test

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PHOS ReadOut Chain DDL

• ALICE Digital Data Link (DDL) the 100 MB/s
  optical link between the detector FEE and the
  first level of the DAQ system (or the High Level
  Trigger system).
• SIU Source Interface Unit
• RORC ReadOut Receiver Card
• PHOS one DDL link per module, i.e. 5 links

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PHOS ReadOut Chain DDL / SIU

• DDL specs for the H/W designers of the detector
  FEE
• SIU on the FEE card, dimensions about 80 x 35
  mm², note height requirement for optical
  transceiver
• below right proto of DIU on the RORC side. Note
  dual fibres for bidirec. traffic.
• below left SIU (courtesy CERN PhotoLab)

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PHOS ReadOut Chain lt-gt ALICE Trigger

• FEE interaction with ALICE Trigger system
• CTP - Central Trigger Processor
• LTC - Local Trigger Crate, a VME crate with the
  Local Trigger Unit, TTC boards, etc.
• TTC the LHC Timing Trigger Control system

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ALICE Trigger protocol

• The ALICE Trigger, baseline
• L0 trigger (signal) 1.2 ?sec Cable from
  Trigger rack
• L1 trigger (signal) 5.2 ?sec TTC optical
  from Trigger rack
• L2a accept (message) up to 100 ?sec Cable
  from Trigger rack - action send data to DAQ over
  DDL
• L2r reject - lt 100 ?sec - Cable to Trigger
  rack

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ALICE Central Trigger Processor

• PHOS connection to the ALICE Trigger System
• Functionalities and requirements see document
  ALICE Central Trigger Processor (CTP) URD
• CTP receives input from ALICE trigger
  sub-detectors and the read-out sub-detectors
  (calibration requests, BUSY) and forms, in each
  bunch crossing interval, L0, L1 and L2 YES/NO
  trigger decisions for all sub-detectors.
• LTC Local Trigger Crate a VME crate, part of
  the sub-detector electronics, contains the LTU
  (Local Trigger Unit), the TTC (Timing, Trigger
  and Control system.
• Taking height for a PHOS Trigger
•        

Requested by PHOS, email from Gines Martinez 08
Feb 2001 to Orlando Villalobos at least one
input at the L1 level, three inputs as an optimal
situation. (The CTP will have a total of 12 (may
have changed?) L1 inputs).
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ALICE Central Trigger Processor

• Proposed CTP lt-gt detector communication

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ALICE Trigger

• The ALICE Trigger chain

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ALICE Trigger Stop Press!

• Recent Web message from the Trigger group
• Last updated 5 September 2001
• For some time now, the ALICE Trigger project has
  been a subject of a major re-definition. The
  requested changes are likely to affect not only
  the Central Trigger Processor, but also the
  interfaces to sub-detectors, the DAQ and the
  Region of Interest system. For that reason, all
  the agreements reached so far and all the written
  documents (URD, Layout and Connections, etc.)
  should be considered no longer valid and will
  have to be re-assessed in the future.
• If your group is in the process of deciding the
  hardware configuration of your system, please
  postpone any "final" decisions until the modified
  definition of the interface becomes available.
• Comments, complaints and compliments to
• p.jovanovic_at_bham.ac.uk
• o.villalobos_at_bham.ac.uk

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ALICE FrontEnd and ReadOut Electronics

• FEE and ROE H/W - where are we

FEM Shaper, MPX,ADC Kurchatov
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ALICE FrontEnd and ReadOut Electronics

• Engineering resources, persons

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ALICE FrontEnd and ReadOut Electronics

• User requirements (add question marks freely at
  the end)
• Front-End Module
• where (on the detector)
• ADC
• 13 bits linear
• fewer bits non-linear
• Multi-Event Buffer
• memory, processing
• FPGAs with MB of memory, CPU cores
• trigger and DDL interface, another FPGA local
  bus
• real estate (geometry)
• VME environment
• Actions
• Needed physics ( political) decisions required
• PHOS trigger, Time-of-Flight,
• US contribution decision urgently needed

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ALICE ReadOut Electronics where ?

• ALICE electronic racks
• ALICE Technical Note 2001-06-08 (C.R. Gregory)
• Rack areas
• Floor of experimental area (UX25), both sides of
  magnet
• Platforms inside experimental area, 12 m above
  floor
• Four levels of counting rooms (PX24)
• Shielding plug level (PX24)
• CERN Standard rack height of 52 units
• Preliminary reservation for PHOS (Klovning)
• 6 racks outside the doors of the L3 magnet
• Subracks (crates) for LHC experiments
• Technical specs by EP LHC Common Crate Project
• VME64 standard
• VME64xP (extension for physics)
• Number of VME crates for PHOS??