Multi core Architecture In Media Processing.

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Multi core Architecture InMedia Processing.
Satani Hasan
Srinivas
Reddy Lokesh Yenneti
Devi Vara
Prasad
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AGENDA

• OVERVIEW OF EXISTING SOLUTIONS
• A BREIF REVIEW OF SOME OF THOSE ARCHITECTURES
• MERITS AND DEMERITS OF THESE ARCHITECTURES
• A MODEL ARCHITECTURE.
• CONCLUSIONS.

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Hibrid SOC
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• Merits
• Computing Efficiency ( Heterogenous Core)
• Simple to Design
• Demerits
• Not adaptable to future Changes

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MLCA Architecture
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• Merits
• Loop Unrolling(Universal Register File)
• Reduced Software Complexity
• Efficient Communication
• Demerits
• Not Adaptable to Future Changes
• No Multi Threading

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Heterogeneous Multi Core

• ISA Processor
• RISC Processor
• Reconfigurable Controller
• Internal Global Data Memory
• Intellectual Property Blocks(HAC)

• Techniques Used
• CLIW
• Parallelism

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Merits Demerits

• Merits
• Flexible
• Heterogeneous
• Parallelism
• Reduced Instruction Size
• Demerits
• Requires Sophisticated Compiler Technology
• No Multi Threading
• No Memory Hierarchy

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Coherent Multi Threading

• Visio MT Processor
• Virtual VLIW , SMT Configurable Architecture

• Techniques Used
• VLIW
• Multithreading
• Parallelism

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• Merits
• Reduced Memory BW
• Fast Data Exchange Reduced Latency
• Uses Coherent Multi Threading
• Memory Hierarchy
• Reduced Bus Overhead
• Reduced Integration Costs
• Demerits
• Non Flexible
• Limited Cores

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What Factor Decides Architecture Efficiency?

• Heterogeneous
• Coherent Multithreading
• Dynamic scheduling
• Memory hierarchy used
• Instruction code generation
• Parallelism
• Bus usage without overhead
• Loop unrolling

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MODEL ARCHITECHTURE

• Is it possible to implement all these techniques
  in one single multi core architecture?
• No

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TECHNIQUES

• Heterogeneousv
• Dynamic schedulingv
• Memory hierarchy v
• Instruction code generationv
• Instruction Level Parallelismv
• Bus usage without overheadv
• Coherent Multithreadingv
• Loop unrolling

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Conclusions !!
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?