10GHz Clock Distribution using Coupled Standingwave Oscillators

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10GHz Clock Distribution using Coupled
Standing-wave Oscillators

• Frank OMahony (fomahony_at_stanford.edu)
• Advisor Professor S. Simon Wong
• Integrated Circuits Lab (ICL)
• Stanford University

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Outline

• I. Proposed 10GHz clock network
• II. Standing-wave oscillators (SWOs)
• III. Clock grids from coupled SWOs
• IV. 10GHz test chip results
• V. Simulated jitter and clock buffer

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Proposed 10GHz global clock network

• Global clock network distributes a 10GHz clock
  through a grid of standing-wave oscillators
  (SWOs)
• SWOs are coupled together and sustain
  synchronous, sinusoidal standing waves across the
  chip
• A single clock source coupled into one oscillator
  injection-locks the entire grid
• Clock buffers convert the signal to a digital
  clock to drive the local networks
• The combination of standing waves and coupled
  oscillators enable low-skew, low-jitter clock
  distribution

Single SWO
Clkinj
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Standing-wave grid waveform

• Standing waves
• ideally zero skew
• amplitude varies with position

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Standing wave oscillator (SWO)

• SWOs compensate for interconnect loss with
  circuitry
• Multiple, identically sized cross-coupled pairs
  provide gain
• Differential transmission lines form a
  distributed tank
• SWOs can be coupled together by connecting their
  interconnects and injection locked to an external
  source
• These (effectively) lossless interconnects
  sustain ideal standing-waves with zero skew

LC oscillator vs. standing-wave oscillator (SWO)
Conditions for oscillation at fclk
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SWO amplitude and skew

• A test chip confirmed low-skew for single SWO
• 8GHz clock (injection locked)
• 0.18µm CMOS process
• 90µm NMOS devices
• 80mW total power
• 4.1 mm TL resonator

Amplitude
Amplitude varies sinusoidally
Phase (ps)
Less than 1ps skew
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Coupled standing-wave oscillators

• Multiple SWOs can be coupled together to form a
  grid by connecting their wires
• Each SWO can be viewed as an injection-locked
  oscillator
• Networks of coupled oscillators have a
  phase-averaging effect that reduces jitter
• A single external clock reference can be injected
  into one of the SWOs to lock the entire grid

Clkinj
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10GHz clock grid test chip

• Fabricated in a 0.18µm, 1.8V CMOS process with
  six AlCu metal levels
• Five cross-coupled pairs per SWO
• Differential microstrip transmission lines,14µm
  wide, 4µm spacing, 3.5µm oxide thickness
• Grid is tunable with MOS varactors, allowed for
  intentional detuning of the grid
• Clock receivers are not integrated due to the
  performance limitations of the devices at 10GHz

Clkinj
0.6mm
1.8mm
90µm/0.18µm cross-coupled pairs
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Skew measurements

• Tuned grid
• Entire grid is tuned with a single control
  voltage
• Worst-case skew 0.6ps
• Detuned grid
• One half of the grid is detuned by 1 (10.1GHz)
• Detuning causes a skew gradient across the grid
• Worst-case skew 3.3ps
• Maximum skew between two adjacent points 1.4ps

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Measuring sub-picosecond skew

• Fold clock grid so timing nodes close together
• Homodyne technique mixes the relative phase
  information down to baseband
• Achieves good phase sensitivity (17mV/ps) and
  resolution (lt0.5ps) with careful on-chip delay
  matching in the timing path

4a
2a
3a
1a
3b
4b
1b
2b
?ref
chip boundary
Voltmeter
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Jitter measurement
Tektronics CSA 803C
SWO clock grid injection-locked at 10.0 GHz
1.4ps rms jitter
HP83711B Signal Generator
Pad (to 50 ? CSA)
50?
Differential open-drain buffer
27µm0.18µm
1.5ps rms jitter
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10GHz test chip
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Jitter simulations for SWO grids

• Coupling together multiple SWOs reduces the
  jitter caused by power supply variations
• Each SWO in a grid is coupled with up to three
  other SWOs
• For the simulated case of a 10 power supply drop
  at one cross-coupled pair, the jitter decreases
  as the grid gets larger

Power supply noise 10 variation with 100ps step
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Clock buffer/converter

• Clock buffer delay must not depend on the
  amplitude of the input, or it will add skew
• LPF removes the harmonics that cause
  amplitude-dependent skew
• Simulated with a 2GHz clock (7 FO4 clock period)
  using 0.18µm device models

Clk
Clk
Clock input
200mV
140mV
Vin
5.9ps skew (1.2 of clock cycle)
Sine-to-square converter
Limiting Amp and LPF
Clock output
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Conclusions

• Ideal, low-skew standing waves can be sustained
  on-chip by compensating for interconnect losses.
• Networks of standing-wave oscillators can be
  coupled together to form a clock network with
  favorable skew and jitter characteristics.
• A standing-wave clock network is feasible in a
  future technology for 10GHz clock distribution.

Current work

• Develop a simple model for the behavior of
  networks of coupled standing-wave oscillators.
• Compare the skew and jitter sensitivities of a
  complete multi-GHz standing-wave clock
  distribution to conventional clock networks.